[PATCH] D153316: [Arch64][SelectionDAG] fix infinite loop caused by legalizing & combining CONCAT_VECTORS

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Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D153316

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/AArch64/aarch64-sve-concat_vectors.ll


Index: llvm/test/CodeGen/AArch64/aarch64-sve-concat_vectors.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/aarch64-sve-concat_vectors.ll
@@ -0,0 +1,18 @@
+; RUN: llc -O3 -mcpu=neoverse-n2 < %s | FileCheck %s
+; CHECK: @allocno_reload_assign
+
+; Function Attrs: nocallback nofree nosync nounwind willreturn writeonly
+declare void @llvm.masked.scatter.nxv16i8.nxv16p0(<vscale x 16 x i8>, <vscale x 16 x ptr>, i32 immarg, <vscale x 16 x i1>) #0
+
+define fastcc i8 @allocno_reload_assign() {
+  br label %1
+
+1:                                                ; preds = %1, %0
+  call void @llvm.masked.scatter.nxv16i8.nxv16p0(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x ptr> zeroinitializer, i32 0, <vscale x 16 x i1> xor (<vscale x 16 x i1> shufflevector (<vscale x 16 x i1> icmp eq (<vscale x 16 x ptr> insertelement (<vscale x 16 x ptr> poison, ptr null, i64 0), <vscale x 16 x ptr> zeroinitializer), <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer), <vscale x 16 x i1> shufflevector (<vscale x 16 x i1> insertelement (<vscale x 16 x i1> poison, i1 true, i32 0), <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer)))
+  br label %1
+}
+
+; uselistorder directives
+uselistorder <vscale x 16 x i1> poison, { 1, 2, 0 }
+
+attributes #0 = { nocallback nofree nosync nounwind willreturn writeonly }
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -23167,7 +23167,19 @@
 
     // If the input is a concat_vectors, just make a larger concat by padding
     // with smaller undefs.
-    if (In.getOpcode() == ISD::CONCAT_VECTORS && In.hasOneUse()) {
+    //
+    // https://github.com/llvm/llvm-project/issues/63322
+    //
+    // We've found an infinite loop caused by legalizing & combining
+    // CONCAT_VECTORS. The legalizing happens in
+    // AArch64TargetLowering::LowerCONCAT_VECTORS() and only when LegalDAG is
+    // true. The corresponding combining happens here.
+    //
+    // To fix the issue, we skip the combining if LegalDAG is true. We also
+    // make sure targets which does not support SVE are not affected by this
+    // change.
+    if (In.getOpcode() == ISD::CONCAT_VECTORS && In.hasOneUse() &&
+        (!In.getValueType().isScalableVector() || !LegalDAG)) {
       unsigned NumOps = N->getNumOperands() * In.getNumOperands();
       SmallVector<SDValue, 4> Ops(In->op_begin(), In->op_end());
       Ops.resize(NumOps, DAG.getUNDEF(Ops[0].getValueType()));


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