[PATCH] D153207: [AArch64] Add patterns for scalar FMUL, FMULX, FMADD, FMSUB

[Sam Tebbs via Phabricator via llvm-commits]

samtebbs added a comment.

Looks worthwhile to me so far but I think the test changes need some clean-up.



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Comment at: llvm/test/CodeGen/AArch64/fp16_intrinsic_lane.ll:444-454
+define dso_local half @t_vmulxh_laneq7_f16(half %a, <8 x half> %b, i32 %lane) {
+; CHECK-LABEL: t_vmulxh_laneq7_f16:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    fmulx h0, h0, v1.h[7]
+; CHECK-NEXT:    ret
+entry:
+  %extract = extractelement <8 x half> %b, i32 7
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Some of the test changes, such as this one being moved and renamed, make it hard to see what has changed. Could you try to reduce the number of such differences?


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  https://reviews.llvm.org/D153207/new/

https://reviews.llvm.org/D153207