[PATCH] D152795: [ARM] generate armv6m eXecute Only (XO) code

[John Brawn via Phabricator via llvm-commits]

john.brawn added inline comments.


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Comment at: llvm/lib/Target/ARM/ARMISelLowering.cpp:3962
+  // use immediate relocations.
+  if (Subtarget->useMovt() || Subtarget->genT1ExecuteOnly()) {
+    if (Subtarget->useMovt())
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This should be genExecuteOnly, as it's not thumb1-specific that we want to avoid generating a constant pool, it's just that up until now execute-only implied useMovt.


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Comment at: llvm/lib/Target/ARM/ARMInstrThumb.td:1613
+let isReMaterializable = 1, isMoveImm = 1, Size = 16, hasNoSchedulingInfo = 1 in
+def t1MOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), NoItinerary,
+                            [(set rGPR:$dst, (i32 imm:$src))]>,
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This should be tMOVi32imm for consistency with everything else (all other 16-bit thumb instructions, or pseudoinstructions that expand to 16-bit thumb instructions, are named tSomething).


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Comment at: llvm/lib/Target/ARM/ARMPredicates.td:227-228
 def GenExecuteOnly : Predicate<"Subtarget->genExecuteOnly()">;
+def GenT1ExecuteOnly : Predicate<"Subtarget->genT1ExecuteOnly()">;
+def DontGenT1ExecuteOnly : Predicate<"!Subtarget->genT1ExecuteOnly()">;
 
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I don't think having a genT1ExecuteOnly predicate is a good idea, as it combines a bunch of things which makes things less clear when looking at the tablegen files. I think what we need is:
 * DontGenExecuteOnly which is just the negation of GenExecuteOnly
 * Patterns that are `Requires<[GenT1ExecuteOnly]>` are instead `Requires<[IsThumb1Only, GenExecuteOnly, DontUseMovt]>`
 * tLDRLIT_ga_abs should have `Requires<[IsThumb, DontUseMovt, DontGenExecuteOnly]>`


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D152795/new/

https://reviews.llvm.org/D152795