[PATCH] D152658: [InstCombine] Change SimplifyDemandedVectorElts to use PoisonElts instead of UndefElts

[Nuno Lopes via Phabricator via llvm-commits]

nlopes added inline comments.


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Comment at: llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp:3102-3105
   case Intrinsic::x86_sse4a_extrqi:
   case Intrinsic::x86_sse4a_insertq:
   case Intrinsic::x86_sse4a_insertqi:
+    PoisonElts.setHighBits(VWidth / 2);
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this change doesn't look correct. The bits are undefined, doesn't seem like you can use poison here.


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Comment at: llvm/test/Transforms/InstCombine/vec_shuffle.ll:1301
 ; CHECK-LABEL: @fmul_splat_constant(
-; CHECK-NEXT:    [[TMP1:%.*]] = fmul <2 x float> [[X:%.*]], <float 4.200000e+01, float poison>
-; CHECK-NEXT:    [[R:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> poison, <2 x i32> zeroinitializer
+  ; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <2 x float> [[X:%.*]], <2 x float> undef, <2 x i32> zeroinitializer
+; CHECK-NEXT:    [[R:%.*]] = fmul <2 x float> [[TMP1]], <float 4.200000e+01, float 4.200000e+01>
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Why does it regress here (goes from poison to undef)?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D152658/new/

https://reviews.llvm.org/D152658