[llvm] 3b8c12c - [AVR][NFC] Improve CodeGen tests

[Ben Shi via llvm-commits]

Author: Ben Shi
Date: 2023-06-11T00:15:20+08:00
New Revision: 3b8c12c18e708cf128e13149991230e47e36b193

URL: https://github.com/llvm/llvm-project/commit/3b8c12c18e708cf128e13149991230e47e36b193
DIFF: https://github.com/llvm/llvm-project/commit/3b8c12c18e708cf128e13149991230e47e36b193.diff

LOG: [AVR][NFC] Improve CodeGen tests

Reviewed By: Patryk27

Differential Revision: https://reviews.llvm.org/D152605

Added: 
    

Modified: 
    llvm/test/CodeGen/AVR/hardware-mul.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/AVR/hardware-mul.ll b/llvm/test/CodeGen/AVR/hardware-mul.ll
index 40e36f9566f89..7e72ead7204ff 100644
--- a/llvm/test/CodeGen/AVR/hardware-mul.ll
+++ b/llvm/test/CodeGen/AVR/hardware-mul.ll
@@ -1,29 +1,40 @@
-; RUN: llc -mattr=mul,movw < %s -march=avr | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -mattr=mul,movw < %s -mtriple=avr | FileCheck %s
 
 ; Tests lowering of multiplication to hardware instructions.
 
 define i8 @mult8(i8 %a, i8 %b) {
 ; CHECK-LABEL: mult8:
-; CHECK: muls r22, r24
-; CHECK: clr r1
-; CHECK: mov  r24, r0
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    muls r22, r24
+; CHECK-NEXT:    clr r1
+; CHECK-NEXT:    mov r24, r0
+; CHECK-NEXT:    ret
   %mul = mul i8 %b, %a
   ret i8 %mul
 }
 
 define i16 @mult16(i16 %a, i16 %b) {
 ; CHECK-LABEL: mult16:
-; CHECK: muls r22, r25
-; CHECK: mov  r20, r0
-; CHECK: mul  r22, r24
-; CHECK: mov  r21, r0
-; CHECK: mov  r18, r1
-; CHECK: clr r1
-; CHECK: add  r18, r20
-; CHECK: muls r23, r24
-; CHECK: clr r1
-; CHECK: add  r18, r0
-; :TODO: finish after reworking shift instructions
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    muls r22, r25
+; CHECK-NEXT:    mov r20, r0
+; CHECK-NEXT:    clr r1
+; CHECK-NEXT:    mul r22, r24
+; CHECK-NEXT:    mov r21, r0
+; CHECK-NEXT:    mov r18, r1
+; CHECK-NEXT:    clr r1
+; CHECK-NEXT:    add r18, r20
+; CHECK-NEXT:    muls r23, r24
+; CHECK-NEXT:    clr r1
+; CHECK-NEXT:    add r18, r0
+; CHECK-NEXT:    mov r19, r18
+; CHECK-NEXT:    clr r18
+; CHECK-NEXT:    mov r24, r21
+; CHECK-NEXT:    clr r25
+; CHECK-NEXT:    or r24, r18
+; CHECK-NEXT:    or r25, r19
+; CHECK-NEXT:    ret
   %mul = mul nsw i16 %b, %a
   ret i16 %mul
 }