[llvm] a5fc989 - [TypePromotion] Don't treat bitcast as a Source

[David Green via llvm-commits]

Author: David Green
Date: 2023-06-09T08:32:26+01:00
New Revision: a5fc9893ac0dcc1d546fde54dd99ae0b92a1108c

URL: https://github.com/llvm/llvm-project/commit/a5fc9893ac0dcc1d546fde54dd99ae0b92a1108c
DIFF: https://github.com/llvm/llvm-project/commit/a5fc9893ac0dcc1d546fde54dd99ae0b92a1108c.diff

LOG: [TypePromotion] Don't treat bitcast as a Source

This removes BitCasts from isSource in Type Promotion, as I don't believe they
need to be treated as Sources. They will usually be from floats or hoisted
constants, where constants will be handled already.

This fixes #62513, but didn't otherwise cause any differences in the tests I
ran.

Differential Revision: https://reviews.llvm.org/D152112

Added: 
    llvm/test/Transforms/TypePromotion/AArch64/bitcast.ll

Modified: 
    llvm/lib/CodeGen/TypePromotion.cpp
    llvm/test/Transforms/TypePromotion/ARM/casts.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/TypePromotion.cpp b/llvm/lib/CodeGen/TypePromotion.cpp
index 028ca7bc25d7b..426292345a147 100644
--- a/llvm/lib/CodeGen/TypePromotion.cpp
+++ b/llvm/lib/CodeGen/TypePromotion.cpp
@@ -235,8 +235,6 @@ bool TypePromotionImpl::isSource(Value *V) {
     return true;
   else if (isa<LoadInst>(V))
     return true;
-  else if (isa<BitCastInst>(V))
-    return true;
   else if (auto *Call = dyn_cast<CallInst>(V))
     return Call->hasRetAttr(Attribute::AttrKind::ZExt);
   else if (auto *Trunc = dyn_cast<TruncInst>(V))
@@ -724,8 +722,9 @@ bool TypePromotionImpl::isSupportedValue(Value *V) {
     case Instruction::Ret:
     case Instruction::Load:
     case Instruction::Trunc:
-    case Instruction::BitCast:
       return isSupportedType(I);
+    case Instruction::BitCast:
+      return I->getOperand(0)->getType() == I->getType();
     case Instruction::ZExt:
       return isSupportedType(I->getOperand(0));
     case Instruction::ICmp:

diff  --git a/llvm/test/Transforms/TypePromotion/AArch64/bitcast.ll b/llvm/test/Transforms/TypePromotion/AArch64/bitcast.ll
new file mode 100644
index 0000000000000..883674a0f64e0
--- /dev/null
+++ b/llvm/test/Transforms/TypePromotion/AArch64/bitcast.ll
@@ -0,0 +1,47 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
+; RUN: opt -mtriple=aarch64 -passes=typepromotion,verify,dce -S %s -o - | FileCheck %s
+
+target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+
+define i1 @v8i8bitcast(<8 x i8> %a) {
+; CHECK-LABEL: define i1 @v8i8bitcast
+; CHECK-SAME: (<8 x i8> [[A:%.*]]) {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[C:%.*]] = icmp slt <8 x i8> [[A]], zeroinitializer
+; CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x i1> [[C]] to i8
+; CHECK-NEXT:    [[N:%.*]] = icmp eq i8 [[TMP0]], 0
+; CHECK-NEXT:    ret i1 [[N]]
+;
+entry:
+  %c = icmp slt <8 x i8> %a, zeroinitializer
+  %0 = bitcast <8 x i1> %c to i8
+  %n = icmp eq i8 %0, 0
+  ret i1 %n
+}
+
+define i1 @halfbitcast() {
+; CHECK-LABEL: define i1 @halfbitcast() {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = bitcast half 0xH8000 to i16
+; CHECK-NEXT:    [[DOTNOT114:%.*]] = icmp eq i16 [[TMP0]], 0
+; CHECK-NEXT:    ret i1 [[DOTNOT114]]
+;
+entry:
+  %0 = bitcast half 0xH8000 to i16
+  %.not114 = icmp eq i16 %0, 0
+  ret i1 %.not114
+}
+
+define i1 @v8i8constant(<8 x i1> %a) {
+; CHECK-LABEL: define i1 @v8i8constant
+; CHECK-SAME: (<8 x i1> [[A:%.*]]) {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = bitcast <8 x i1> <i1 true, i1 true, i1 true, i1 false, i1 true, i1 true, i1 true, i1 true> to i8
+; CHECK-NEXT:    [[DOTNOT114:%.*]] = icmp eq i8 [[TMP0]], 0
+; CHECK-NEXT:    ret i1 [[DOTNOT114]]
+;
+entry:
+  %0 = bitcast <8 x i1> <i1 1, i1 1, i1 1, i1 0, i1 1, i1 1, i1 1, i1 1> to i8
+  %.not114 = icmp eq i8 %0, 0
+  ret i1 %.not114
+}

diff  --git a/llvm/test/Transforms/TypePromotion/ARM/casts.ll b/llvm/test/Transforms/TypePromotion/ARM/casts.ll
index 3f0e545bda6ea..cd25347c095cb 100644
--- a/llvm/test/Transforms/TypePromotion/ARM/casts.ll
+++ b/llvm/test/Transforms/TypePromotion/ARM/casts.ll
@@ -248,10 +248,9 @@ define i16 @bitcast_i16(i16 zeroext %arg0, i16 zeroext %arg1) {
 ; CHECK-LABEL: @bitcast_i16(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[ARG0:%.*]] to i32
-; CHECK-NEXT:    [[CAST:%.*]] = bitcast i16 12345 to i16
-; CHECK-NEXT:    [[TMP1:%.*]] = zext i16 [[CAST]] to i32
+; CHECK-NEXT:    [[CAST:%.*]] = bitcast i32 12345 to i32
 ; CHECK-NEXT:    [[ADD:%.*]] = add nuw i32 [[TMP0]], 1
-; CHECK-NEXT:    [[CMP:%.*]] = icmp ule i32 [[ADD]], [[TMP1]]
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ule i32 [[ADD]], [[CAST]]
 ; CHECK-NEXT:    [[RES:%.*]] = select i1 [[CMP]], i16 [[ARG1:%.*]], i16 32657
 ; CHECK-NEXT:    ret i16 [[RES]]
 ;
@@ -1105,3 +1104,30 @@ exit:
   %res = phi float [ 0.0, %entry ], [ %div, %if.end ]
   ret float %res
 }
+
+define i32 @bitcasted() {
+; CHECK-LABEL: @bitcasted(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    br label [[LOOP:%.*]]
+; CHECK:       loop:
+; CHECK-NEXT:    [[T157_PH:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[T145_OLD:%.*]], [[LATCH:%.*]] ]
+; CHECK-NEXT:    [[EXT:%.*]] = zext i32 [[T157_PH]] to i64
+; CHECK-NEXT:    br label [[LATCH]]
+; CHECK:       latch:
+; CHECK-NEXT:    [[T145_OLD]] = bitcast i32 8 to i32
+; CHECK-NEXT:    [[T146_OLD:%.*]] = bitcast i32 [[T145_OLD]] to i32
+; CHECK-NEXT:    br label [[LOOP]]
+;
+entry:
+  br label %loop
+
+loop:
+  %t157.ph = phi i32 [ 0, %entry ], [ %t145.old, %latch ]
+  %ext = zext i32 %t157.ph to i64
+  br label %latch
+
+latch:
+  %t145.old = bitcast i32 8 to i32
+  %t146.old = bitcast i32 %t145.old to i32
+  br label %loop
+}