[PATCH] D151396: [2/N][RISCV] Model vxrm in LLVM intrinsics and machine instructions for RVV fixed-point instructions
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 8 08:57:41 PDT 2023
craig.topper added inline comments.
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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:1190
+class VPseudoBinaryNoMaskTURoundingMode<VReg RetClass,
+ VReg Op1Class,
+ DAGOperand Op2Class,
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Indentation
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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:2038
+multiclass VPseudoBinaryRoundingMode<VReg RetClass,
+ VReg Op1Class,
+ DAGOperand Op2Class,
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Indentation
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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:4781
+multiclass VPatBinaryTARoundingMode<string intrinsic,
+ string inst,
+ ValueType result_type,
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Indentation
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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:4928
+multiclass VPatBinaryV_VVRoundingMode<string intrinsic, string instruction,
+ list<VTypeInfo> vtilist> {
+ foreach vti = vtilist in
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Indentation
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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:4995
+multiclass VPatBinaryV_VXRoundingMode<string intrinsic, string instruction,
+ list<VTypeInfo> vtilist> {
+ foreach vti = vtilist in {
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Indentation
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D151396/new/
https://reviews.llvm.org/D151396
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