[PATCH] D152059: [AVR] Replace shift-to-loop IR pass with common shift code

[Ayke via Phabricator via llvm-commits]

aykevl added inline comments.


================
Comment at: llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp:263
+
+    if (isLogicRegOpUndef(Op, Lo8)) {
+      MIBLO->getOperand(1).setIsUndef(true);
----------------
benshi001 wrote:
> Why `and` with zero should be special? Could you please give an example? Or add a test .ll ?
This is part of subreg liveness: https://github.com/aykevl/llvm-project/commit/8af44a965e16a16c4edd4e01143ab1c260e3d924

I don't remember exactly why this was needed but I think the machine verifier complained otherwise.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D152059/new/

https://reviews.llvm.org/D152059