[llvm] 0535da6 - [InstCombine] Add test case for (icmp eq A, -1) & (icmp eq B, -1) --> (icmp eq (A&B), -1); NFC
Shivam Gupta via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 7 20:37:16 PDT 2023
Author: Shivam Gupta
Date: 2023-06-08T09:00:02+05:30
New Revision: 0535da6f11d7b87102844b905ad3f75b59c9e831
URL: https://github.com/llvm/llvm-project/commit/0535da6f11d7b87102844b905ad3f75b59c9e831
DIFF: https://github.com/llvm/llvm-project/commit/0535da6f11d7b87102844b905ad3f75b59c9e831.diff
LOG: [InstCombine] Add test case for (icmp eq A, -1) & (icmp eq B, -1) --> (icmp eq (A&B), -1); NFC
Reviewed By: goldstein.w.n
Differential Revision: https://reviews.llvm.org/D151694
Added:
llvm/test/Transforms/PhaseOrdering/pr62311.ll
Modified:
llvm/test/Transforms/InstCombine/and-or-icmps.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/InstCombine/and-or-icmps.ll b/llvm/test/Transforms/InstCombine/and-or-icmps.ll
index 163b13a266cf7..2cf2370dc9ca5 100644
--- a/llvm/test/Transforms/InstCombine/and-or-icmps.ll
+++ b/llvm/test/Transforms/InstCombine/and-or-icmps.ll
@@ -2494,3 +2494,80 @@ define i1 @samesign_inverted_wrong_cmp(i32 %x, i32 %y) {
%r = and i1 %gt, %lt
ret i1 %r
}
+
+define <2 x i1> @icmp_eq_m1_and_eq_m1(<2 x i8> %x, <2 x i8> %y) {
+; CHECK-LABEL: @icmp_eq_m1_and_eq_m1(
+; CHECK-NEXT: [[RX:%.*]] = icmp eq <2 x i8> [[X:%.*]], <i8 -1, i8 undef>
+; CHECK-NEXT: [[RY:%.*]] = icmp eq <2 x i8> [[Y:%.*]], <i8 -1, i8 undef>
+; CHECK-NEXT: [[R:%.*]] = and <2 x i1> [[RX]], [[RY]]
+; CHECK-NEXT: ret <2 x i1> [[R]]
+;
+ %rx = icmp eq <2 x i8> %x, <i8 -1, i8 undef>
+ %ry = icmp eq <2 x i8> %y, <i8 -1, i8 undef>
+ %r = and <2 x i1> %rx, %ry
+ ret <2 x i1> %r
+}
+
+define <2 x i1> @icmp_eq_m1_and_eq_undef_m1(<2 x i8> %x, <2 x i8> %y) {
+; CHECK-LABEL: @icmp_eq_m1_and_eq_undef_m1(
+; CHECK-NEXT: [[RX:%.*]] = icmp eq <2 x i8> [[X:%.*]], <i8 -1, i8 undef>
+; CHECK-NEXT: [[RY:%.*]] = icmp eq <2 x i8> [[Y:%.*]], <i8 undef, i8 -1>
+; CHECK-NEXT: [[R:%.*]] = and <2 x i1> [[RX]], [[RY]]
+; CHECK-NEXT: ret <2 x i1> [[R]]
+;
+ %rx = icmp eq <2 x i8> %x, <i8 -1, i8 undef>
+ %ry = icmp eq <2 x i8> %y, <i8 undef, i8 -1>
+ %r = and <2 x i1> %rx, %ry
+ ret <2 x i1> %r
+}
+
+define <2 x i1> @icmp_eq_undef_and_eq_m1_m2(<2 x i8> %x, <2 x i8> %y) {
+; CHECK-LABEL: @icmp_eq_undef_and_eq_m1_m2(
+; CHECK-NEXT: ret <2 x i1> zeroinitializer
+;
+ %rx = icmp eq <2 x i8> %x, <i8 undef, i8 undef>
+ %ry = icmp eq <2 x i8> %y, <i8 -1, i8 -2>
+ %r = and <2 x i1> %rx, %ry
+ ret <2 x i1> %r
+}
+
+define <2 x i1> @icmp_ne_m1_and_ne_m1_fail(<2 x i8> %x, <2 x i8> %y) {
+; CHECK-LABEL: @icmp_ne_m1_and_ne_m1_fail(
+; CHECK-NEXT: [[RX:%.*]] = icmp ne <2 x i8> [[X:%.*]], <i8 -1, i8 undef>
+; CHECK-NEXT: [[RY:%.*]] = icmp ne <2 x i8> [[Y:%.*]], <i8 -1, i8 undef>
+; CHECK-NEXT: [[R:%.*]] = and <2 x i1> [[RX]], [[RY]]
+; CHECK-NEXT: ret <2 x i1> [[R]]
+;
+ %rx = icmp ne <2 x i8> %x, <i8 -1, i8 undef>
+ %ry = icmp ne <2 x i8> %y, <i8 -1, i8 undef>
+ %r = and <2 x i1> %rx, %ry
+ ret <2 x i1> %r
+}
+
+
+define <2 x i1> @icmp_eq_m1_or_eq_m1_fail(<2 x i8> %x, <2 x i8> %y) {
+; CHECK-LABEL: @icmp_eq_m1_or_eq_m1_fail(
+; CHECK-NEXT: [[RX:%.*]] = icmp eq <2 x i8> [[X:%.*]], <i8 -1, i8 undef>
+; CHECK-NEXT: [[RY:%.*]] = icmp eq <2 x i8> [[Y:%.*]], <i8 -1, i8 undef>
+; CHECK-NEXT: [[R:%.*]] = or <2 x i1> [[RX]], [[RY]]
+; CHECK-NEXT: ret <2 x i1> [[R]]
+;
+ %rx = icmp eq <2 x i8> %x, <i8 -1, i8 undef>
+ %ry = icmp eq <2 x i8> %y, <i8 -1, i8 undef>
+ %r = or <2 x i1> %rx, %ry
+ ret <2 x i1> %r
+}
+
+
+define <2 x i1> @icmp_ne_m1_or_ne_m1(<2 x i8> %x, <2 x i8> %y) {
+; CHECK-LABEL: @icmp_ne_m1_or_ne_m1(
+; CHECK-NEXT: [[RX:%.*]] = icmp ne <2 x i8> [[X:%.*]], <i8 -1, i8 -1>
+; CHECK-NEXT: [[RY:%.*]] = icmp ne <2 x i8> [[Y:%.*]], <i8 -1, i8 undef>
+; CHECK-NEXT: [[R:%.*]] = or <2 x i1> [[RX]], [[RY]]
+; CHECK-NEXT: ret <2 x i1> [[R]]
+;
+ %rx = icmp ne <2 x i8> %x, <i8 -1, i8 -1>
+ %ry = icmp ne <2 x i8> %y, <i8 -1, i8 undef>
+ %r = or <2 x i1> %rx, %ry
+ ret <2 x i1> %r
+}
diff --git a/llvm/test/Transforms/PhaseOrdering/pr62311.ll b/llvm/test/Transforms/PhaseOrdering/pr62311.ll
new file mode 100644
index 0000000000000..01d6383c9f82a
--- /dev/null
+++ b/llvm/test/Transforms/PhaseOrdering/pr62311.ll
@@ -0,0 +1,80 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -passes='default<O3>' -S | FileCheck %s
+
+; C++ version of test case
+; #include <x86intrin.h>
+;
+; bool allones(__m512i x) {
+; return
+; x[0] == -1 && x[1] == -1 &&
+; x[2] == -1 && x[3] == -1 &&
+; x[4] == -1 && x[5] == -1 &&
+; x[6] == -1 && x[7] == -1;
+; }
+
+target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+; Function Attrs: mustprogress nounwind uwtable
+define noundef zeroext i1 @allones(<8 x i64> noundef %x) {
+; CHECK-LABEL: @allones(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[VECEXT:%.*]] = extractelement <8 x i64> [[X:%.*]], i64 0
+; CHECK-NEXT: [[VECEXT1:%.*]] = extractelement <8 x i64> [[X]], i64 1
+; CHECK-NEXT: [[TMP0:%.*]] = and i64 [[VECEXT]], [[VECEXT1]]
+; CHECK-NEXT: [[OR_COND:%.*]] = icmp eq i64 [[TMP0]], -1
+; CHECK-NEXT: [[VECEXT4:%.*]] = extractelement <8 x i64> [[X]], i64 2
+; CHECK-NEXT: [[VECEXT7:%.*]] = extractelement <8 x i64> [[X]], i64 3
+; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[VECEXT4]], [[VECEXT7]]
+; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], -1
+; CHECK-NEXT: [[OR_COND21:%.*]] = and i1 [[OR_COND]], [[TMP2]]
+; CHECK-NEXT: [[VECEXT10:%.*]] = extractelement <8 x i64> [[X]], i64 4
+; CHECK-NEXT: [[VECEXT13:%.*]] = extractelement <8 x i64> [[X]], i64 5
+; CHECK-NEXT: [[TMP3:%.*]] = and i64 [[VECEXT10]], [[VECEXT13]]
+; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[TMP3]], -1
+; CHECK-NEXT: [[OR_COND23:%.*]] = and i1 [[TMP4]], [[OR_COND21]]
+; CHECK-NEXT: [[VECEXT16:%.*]] = extractelement <8 x i64> [[X]], i64 6
+; CHECK-NEXT: [[CMP17:%.*]] = icmp eq i64 [[VECEXT16]], -1
+; CHECK-NEXT: [[OR_COND24:%.*]] = and i1 [[CMP17]], [[OR_COND23]]
+; CHECK-NEXT: br i1 [[OR_COND24]], label [[LAND_RHS:%.*]], label [[LAND_END:%.*]]
+; CHECK: land.rhs:
+; CHECK-NEXT: [[VECEXT18:%.*]] = extractelement <8 x i64> [[X]], i64 7
+; CHECK-NEXT: [[CMP19:%.*]] = icmp eq i64 [[VECEXT18]], -1
+; CHECK-NEXT: br label [[LAND_END]]
+; CHECK: land.end:
+; CHECK-NEXT: [[TMP5:%.*]] = phi i1 [ false, [[ENTRY:%.*]] ], [ [[CMP19]], [[LAND_RHS]] ]
+; CHECK-NEXT: ret i1 [[TMP5]]
+;
+entry:
+ %vecext = extractelement <8 x i64> %x, i32 0
+ %cmp = icmp eq i64 %vecext, -1
+ %vecext1 = extractelement <8 x i64> %x, i32 1
+ %cmp2 = icmp eq i64 %vecext1, -1
+ %or.cond = select i1 %cmp, i1 %cmp2, i1 false
+ %vecext4 = extractelement <8 x i64> %x, i32 2
+ %cmp5 = icmp eq i64 %vecext4, -1
+ %or.cond20 = select i1 %or.cond, i1 %cmp5, i1 false
+ %vecext7 = extractelement <8 x i64> %x, i32 3
+ %cmp8 = icmp eq i64 %vecext7, -1
+ %or.cond21 = select i1 %or.cond20, i1 %cmp8, i1 false
+ %vecext10 = extractelement <8 x i64> %x, i32 4
+ %cmp11 = icmp eq i64 %vecext10, -1
+ %or.cond22 = select i1 %or.cond21, i1 %cmp11, i1 false
+ %vecext13 = extractelement <8 x i64> %x, i32 5
+ %cmp14 = icmp eq i64 %vecext13, -1
+ %or.cond23 = select i1 %or.cond22, i1 %cmp14, i1 false
+ %vecext16 = extractelement <8 x i64> %x, i32 6
+ %cmp17 = icmp eq i64 %vecext16, -1
+ %or.cond24 = select i1 %or.cond23, i1 %cmp17, i1 false
+ br i1 %or.cond24, label %land.rhs, label %land.end
+
+land.rhs: ; preds = %entry
+ %vecext18 = extractelement <8 x i64> %x, i32 7
+
+ %cmp19 = icmp eq i64 %vecext18, -1
+ br label %land.end
+
+land.end: ; preds = %land.rhs, %entry
+ %0 = phi i1 [ false, %entry ], [ %cmp19, %land.rhs ]
+ ret i1 %0
+}
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