[llvm] b03e6e6 - [RISCV] Change riscv_vid_vl isel pattern to use _MASK instruction.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-06-07T12:50:26-07:00
New Revision: b03e6e65e7430e032fca58f0982d1918a0ccba08

URL: https://github.com/llvm/llvm-project/commit/b03e6e65e7430e032fca58f0982d1918a0ccba08
DIFF: https://github.com/llvm/llvm-project/commit/b03e6e65e7430e032fca58f0982d1918a0ccba08.diff

LOG: [RISCV] Change riscv_vid_vl isel pattern to use _MASK instruction.

The post isel peephole can convert it to the unmasked form.

We don't have any way to test the masked version right now because
we always use a true mask.

This makes the isel pattern consistent with many other instructions
that select the mask form.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
index 71df6e4a6fce2..aecfab66708c3 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
@@ -2476,9 +2476,11 @@ def riscv_fslide1down_vl  : SDNode<"RISCVISD::VFSLIDE1DOWN_VL", SDTRVVFSlide1, [
 
 foreach vti = AllIntegerVectors in {
   let Predicates = GetVTypePredicates<vti>.Predicates in {
-    def : Pat<(vti.Vector (riscv_vid_vl (vti.Mask true_mask),
+    def : Pat<(vti.Vector (riscv_vid_vl (vti.Mask V0),
                                         VLOpFrag)),
-              (!cast<Instruction>("PseudoVID_V_"#vti.LMul.MX) GPR:$vl, vti.Log2SEW)>;
+              (!cast<Instruction>("PseudoVID_V_"#vti.LMul.MX#"_MASK")
+                  (vti.Vector (IMPLICIT_DEF)), (vti.Mask V0), GPR:$vl, vti.Log2SEW,
+                  TAIL_AGNOSTIC)>;
 
     def : Pat<(vti.Vector (riscv_slide1up_vl (vti.Vector undef),
                                              (vti.Vector vti.RegClass:$rs1),