[PATCH] D152376: [RISCV][Cost] Add VectorToScalarBaseCost for extractelement

[ShihPo Hung via Phabricator via llvm-commits]

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This patch proposes an alternative approach to D152001 <https://reviews.llvm.org/D152001> to prevent
unprofitable decisions made by the vectorizer for small VF.
Some CPU implementations have high cost when performing vector-to-scalar communication,
For example, consider the given reduction operation with VF=4:

  vle32.v v0, (a5)
  vmv.s.x v8, a0
  vfredusum.vs v8, v0, v8
  vfmv.f.s fa0, v8

Despite that `vle32.v` and `vfredsum.vs` instructions have higher throughput than scalar does,
the profitability is hindered when the vector-to-scalar communication cost is excessively
high.
To address this, the patch introduces an interface within the subtarget,
enabling individual CPUs to differentiate the associated costs.
This approach mirrors VectorInsertExtractBaseCost used in AArch64 .


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D152376

Files:
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
  llvm/test/Analysis/CostModel/RISCV/fixed-vector-scatter.ll
  llvm/test/Analysis/CostModel/RISCV/rvv-extractelement.ll
  llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll

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