[PATCH] D152368: [RISCV] Use vslidedown.vi vN, vN, 0 instead of vslideup.vi vN, vM, 0

[Luke Lau via Phabricator via llvm-commits]

luke created this revision.
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These instructions are semantically identical in the case where the
offset is 0 with the exception that vslideup has a vector overlap
constraint and vslidedown doesn't. As a result, we can prefer the one
without register overlap constraints to improve register allocation
flexibility.

This patch implements https://reviews.llvm.org/D152298 but as a DAG
combine. It catches a few more cases, including some scalable vectors.

Co-authored-by: preames at rivosinc.com


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D152368

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
  llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll
  llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
  llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll

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