[llvm] 3d0350b - AMDGPU: Add MF independent version of getImplicitParameterOffset
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 7 05:26:37 PDT 2023
Author: Matt Arsenault
Date: 2023-06-07T08:26:31-04:00
New Revision: 3d0350b762959af8ae239938651e780a84d987cc
URL: https://github.com/llvm/llvm-project/commit/3d0350b762959af8ae239938651e780a84d987cc
DIFF: https://github.com/llvm/llvm-project/commit/3d0350b762959af8ae239938651e780a84d987cc.diff
LOG: AMDGPU: Add MF independent version of getImplicitParameterOffset
Added:
Modified:
llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
llvm/lib/Target/AMDGPU/AMDGPULowerKernelArguments.cpp
llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
index 36f52c772aea1..6d79f27c263f0 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
@@ -521,7 +521,7 @@ bool AMDGPUCallLowering::lowerFormalArgumentsKernel(
unsigned i = 0;
const Align KernArgBaseAlign(16);
- const unsigned BaseOffset = Subtarget->getExplicitKernelArgOffset(F);
+ const unsigned BaseOffset = Subtarget->getExplicitKernelArgOffset();
uint64_t ExplicitArgOffset = 0;
// TODO: Align down to dword alignment and extract bits for extending loads.
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index d08f2aaa9794f..c0f75d17dd231 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -1066,7 +1066,7 @@ void AMDGPUTargetLowering::analyzeFormalArgumentsCompute(
const Function &Fn = MF.getFunction();
LLVMContext &Ctx = Fn.getParent()->getContext();
const AMDGPUSubtarget &ST = AMDGPUSubtarget::get(MF);
- const unsigned ExplicitOffset = ST.getExplicitKernelArgOffset(Fn);
+ const unsigned ExplicitOffset = ST.getExplicitKernelArgOffset();
CallingConv::ID CC = Fn.getCallingConv();
Align MaxAlign = Align(1);
@@ -4563,13 +4563,11 @@ SDValue AMDGPUTargetLowering::loadInputValue(SelectionDAG &DAG,
}
uint32_t AMDGPUTargetLowering::getImplicitParameterOffset(
- const MachineFunction &MF, const ImplicitParameter Param) const {
- const AMDGPUMachineFunction *MFI = MF.getInfo<AMDGPUMachineFunction>();
- unsigned ExplicitArgOffset =
- Subtarget->getExplicitKernelArgOffset(MF.getFunction());
+ uint64_t ExplicitKernArgSize, const ImplicitParameter Param) const {
+ unsigned ExplicitArgOffset = Subtarget->getExplicitKernelArgOffset();
const Align Alignment = Subtarget->getAlignmentForImplicitArgPtr();
- uint64_t ArgOffset = alignTo(MFI->getExplicitKernArgSize(), Alignment) +
- ExplicitArgOffset;
+ uint64_t ArgOffset =
+ alignTo(ExplicitKernArgSize, Alignment) + ExplicitArgOffset;
switch (Param) {
case FIRST_IMPLICIT:
return ArgOffset;
@@ -4583,6 +4581,12 @@ uint32_t AMDGPUTargetLowering::getImplicitParameterOffset(
llvm_unreachable("unexpected implicit parameter type");
}
+uint32_t AMDGPUTargetLowering::getImplicitParameterOffset(
+ const MachineFunction &MF, const ImplicitParameter Param) const {
+ const AMDGPUMachineFunction *MFI = MF.getInfo<AMDGPUMachineFunction>();
+ return getImplicitParameterOffset(MFI->getExplicitKernArgSize(), Param);
+}
+
#define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;
const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
index 99bb63b40c8be..bc35c4ea0b3ea 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
@@ -344,6 +344,8 @@ class AMDGPUTargetLowering : public TargetLowering {
/// type of implicit parameter.
uint32_t getImplicitParameterOffset(const MachineFunction &MF,
const ImplicitParameter Param) const;
+ uint32_t getImplicitParameterOffset(const uint64_t ExplicitKernArgSize,
+ const ImplicitParameter Param) const;
MVT getFenceOperandTy(const DataLayout &DL) const override {
return MVT::i32;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULowerKernelArguments.cpp b/llvm/lib/Target/AMDGPU/AMDGPULowerKernelArguments.cpp
index eb57203c6aee0..f5323725250f3 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULowerKernelArguments.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULowerKernelArguments.cpp
@@ -70,7 +70,7 @@ bool AMDGPULowerKernelArguments::runOnFunction(Function &F) {
IRBuilder<> Builder(&*getInsertPt(EntryBlock));
const Align KernArgBaseAlign(16); // FIXME: Increase if necessary
- const uint64_t BaseOffset = ST.getExplicitKernelArgOffset(F);
+ const uint64_t BaseOffset = ST.getExplicitKernelArgOffset();
Align MaxAlign;
// FIXME: Alignment is broken with explicit arg offset.;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
index 9fe5801ad7a45..ad2328c802e27 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
@@ -576,7 +576,7 @@ unsigned AMDGPUSubtarget::getKernArgSegmentSize(const Function &F,
Align &MaxAlign) const {
uint64_t ExplicitArgBytes = getExplicitKernArgSize(F, MaxAlign);
- unsigned ExplicitOffset = getExplicitKernelArgOffset(F);
+ unsigned ExplicitOffset = getExplicitKernelArgOffset();
uint64_t TotalSize = ExplicitOffset + ExplicitArgBytes;
unsigned ImplicitBytes = getImplicitArgNumBytes(F);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
index 9c1407cb26f53..f9d33cb9e47a2 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
@@ -226,7 +226,7 @@ class AMDGPUSubtarget {
/// Returns the offset in bytes from the start of the input buffer
/// of the first explicit kernel argument.
- unsigned getExplicitKernelArgOffset(const Function &F) const {
+ unsigned getExplicitKernelArgOffset() const {
switch (TargetTriple.getOS()) {
case Triple::AMDHSA:
case Triple::AMDPAL:
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