[PATCH] D152342: [PowerPC] calculate sadd/ssub overflow by sign bits

[Ting Wang via Phabricator via llvm-commits]

tingwang created this revision.
tingwang added reviewers: shchenz, nemanjai, PowerPC.
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This patch propose to calculate overflow by using sign bits.

Take signed-add as example: (`LHS` + `RHS` = `Result`), the original approach compare `Result` with `LHS` (this compare could involve multiple bits of information), and `RHS` with `0`. 
@llvm.sadd.with.overflow.i64 generates following instructions on P9 <https://reviews.llvm.org/P9>:

  ld 3, 0(3)
  ld 4, 0(4)
  add 6, 3, 4
  rldicl 8, 3, 1, 63
  rldicl 4, 4, 1, 63
  sradi 7, 6, 63
  subc    3, 6, 3
  std 6, 0(5)
  adde 3, 8, 7
  xori 3, 3, 1
  xor 3, 4, 3
  blr

Alternative approach proposed here only use sign bits from `LHS`, `RHS`, and `Result` to decide overflow condition.

  ld 3, 0(3)
  ld 4, 0(4)
  add 6, 3, 4
  xor 4, 4, 6
  xor 3, 3, 6
  std 6, 0(5)
  and 3, 3, 4
  rldicl 3, 3, 1, 63
  blr


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D152342

Files:
  llvm/include/llvm/CodeGen/TargetLowering.h
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.h
  llvm/test/CodeGen/PowerPC/saddo-ssubo.ll

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