[llvm] 2a8df8d - [AArch64][SVE] Add one-use-check to EitherVSelectOrPassthruPatFrags

[David Green via llvm-commits]

Author: David Green
Date: 2023-06-06T21:10:32+01:00
New Revision: 2a8df8d0b9e1cf132862aa8782bb99b4039feb89

URL: https://github.com/llvm/llvm-project/commit/2a8df8d0b9e1cf132862aa8782bb99b4039feb89
DIFF: https://github.com/llvm/llvm-project/commit/2a8df8d0b9e1cf132862aa8782bb99b4039feb89.diff

LOG: [AArch64][SVE] Add one-use-check to EitherVSelectOrPassthruPatFrags

As pointed out in D149968 vselect predicate patterns could do with a one-use
check to prevent multiple operations being created. This updates the
EitherVSelectOrPassthruPatFrags pattern frags used in creating predicates
min/max.

Differential Revision: https://reviews.llvm.org/D151080

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/SVEInstrFormats.td
    llvm/test/CodeGen/AArch64/sve-min-max-pred.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td
index f9c37678c2322..3cb9e0c5d9061 100644
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -635,7 +635,9 @@ class EitherVSelectOrPassthruPatFrags<SDPatternOperator intrinsic, SDPatternOper
 : PatFrags<(ops node:$Pg, node:$Op1, node:$Op2), [
     (intrinsic node:$Pg, node:$Op1, node:$Op2),
     (vselect node:$Pg, (sdnode (SVEAllActive), node:$Op1, node:$Op2), node:$Op1),
-  ]>;
+  ], [{
+    return N->getOpcode() != ISD::VSELECT || N->getOperand(1).hasOneUse();
+  }]>;
 
 //
 // Pseudo -> Instruction mappings

diff  --git a/llvm/test/CodeGen/AArch64/sve-min-max-pred.ll b/llvm/test/CodeGen/AArch64/sve-min-max-pred.ll
index 8558620080be5..4f56eeac643ee 100644
--- a/llvm/test/CodeGen/AArch64/sve-min-max-pred.ll
+++ b/llvm/test/CodeGen/AArch64/sve-min-max-pred.ll
@@ -177,10 +177,9 @@ define <vscale x 2 x i64> @umin_select_i64_multiuse(<vscale x 2 x i1> %pg, <vsca
 ; CHECK-LABEL: umin_select_i64_multiuse:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p1.d
-; CHECK-NEXT:    movprfx z2, z0
-; CHECK-NEXT:    umin z2.d, p1/m, z2.d, z1.d
-; CHECK-NEXT:    umin z0.d, p0/m, z0.d, z1.d
-; CHECK-NEXT:    st1d { z2.d }, p1, [x0]
+; CHECK-NEXT:    umin z1.d, p1/m, z1.d, z0.d
+; CHECK-NEXT:    mov z0.d, p0/m, z1.d
+; CHECK-NEXT:    st1d { z1.d }, p1, [x0]
 ; CHECK-NEXT:    ret
   %sel = call <vscale x 2 x i64> @llvm.umin.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)
   store <vscale x 2 x i64> %sel, ptr %p