[PATCH] D152293: [RISCV] Use PACK in RISCVMatInt for constants that have the same lower and upper 32 bits.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp:246
+  // If the Low and High halves are the same, use PACK.
+  if (Res.size() > 2 && ActiveFeatures[RISCV::FeatureStdExtZbkb]) {
+    int64_t LoVal = SignExtend64<32>(Val);
----------------
reames wrote:
> "The pack instruction packs the XLEN/2-bit lower halves of rs1 and rs2 into rd, with rs1 in the lower half and
> rs2 in the upper half." 
> 
> I think what you have happens to work since we can always generate a 2 instruction sequence for XLEN=32.  Can you add an assert which shows we only hit this on 64 bit?
I think the 64 bit comment is better addressed by D152300


Repository:
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  https://reviews.llvm.org/D152293/new/

https://reviews.llvm.org/D152293