[PATCH] D152298: [RISCV] Use vslidedown.vi vN, vN, 0 instead of vslideup.vi vN, vM, 0 for subvector insertion

[Philip Reames via Phabricator via llvm-commits]

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These instructions are semantically identical in the case where the offset is 0 with the exception that vslideup has a vector overlap constraint and vslidedown doesn't.  As a result, we can prefer the one without register overlap constraints to improve register allocation flexibility.

This patch is specific to subvector insertion, but this pattern may show up elsewhere.  We could possibly rework this as a DAG combine if reviewers thought that was worthwhile.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D152298

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
  llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll
  llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll

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