[llvm] 9a81b69 - [AArch64] Regenerate tests with missing immediate hex asm comments
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 6 11:47:43 PDT 2023
Author: Simon Pilgrim
Date: 2023-06-06T19:44:28+01:00
New Revision: 9a81b697575244fb8a2f2e24188381c5d69f7bbe
URL: https://github.com/llvm/llvm-project/commit/9a81b697575244fb8a2f2e24188381c5d69f7bbe
DIFF: https://github.com/llvm/llvm-project/commit/9a81b697575244fb8a2f2e24188381c5d69f7bbe.diff
LOG: [AArch64] Regenerate tests with missing immediate hex asm comments
Reduces diff in a future commit
Added:
Modified:
llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.ll
llvm/test/CodeGen/AArch64/addsub-constant-folding.ll
llvm/test/CodeGen/AArch64/sink-addsub-of-const.ll
llvm/test/CodeGen/AArch64/urem-seteq-illegal-types.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.ll b/llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.ll
index 35b02f4d8af9a..395a4a8b87de2 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.ll
@@ -6,7 +6,7 @@
define <8 x i16> @combine_vec_udiv_uniform(<8 x i16> %x) {
; SDAG-LABEL: combine_vec_udiv_uniform:
; SDAG: // %bb.0:
-; SDAG-NEXT: mov w8, #25645
+; SDAG-NEXT: mov w8, #25645 // =0x642d
; SDAG-NEXT: dup v1.8h, w8
; SDAG-NEXT: umull2 v2.4s, v0.8h, v1.8h
; SDAG-NEXT: umull v1.4s, v0.4h, v1.4h
diff --git a/llvm/test/CodeGen/AArch64/addsub-constant-folding.ll b/llvm/test/CodeGen/AArch64/addsub-constant-folding.ll
index 0509e2f5c06f0..af760714d928e 100644
--- a/llvm/test/CodeGen/AArch64/addsub-constant-folding.ll
+++ b/llvm/test/CodeGen/AArch64/addsub-constant-folding.ll
@@ -163,7 +163,7 @@ define <4 x i32> @vec_add_const_sub_const_nonsplat(<4 x i32> %arg) {
define i32 @add_const_const_sub(i32 %arg) {
; CHECK-LABEL: add_const_const_sub:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #-6
+; CHECK-NEXT: mov w8, #-6 // =0xfffffffa
; CHECK-NEXT: sub w0, w8, w0
; CHECK-NEXT: ret
%t0 = add i32 %arg, 8
@@ -181,7 +181,7 @@ define i32 @add_const_const_sub_extrause(i32 %arg) {
; CHECK-NEXT: mov w19, w0
; CHECK-NEXT: add w0, w0, #8
; CHECK-NEXT: bl use
-; CHECK-NEXT: mov w8, #-6
+; CHECK-NEXT: mov w8, #-6 // =0xfffffffa
; CHECK-NEXT: sub w0, w8, w19
; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: ret
@@ -396,7 +396,7 @@ define <4 x i32> @vec_sub_const_sub_const_nonsplat(<4 x i32> %arg) {
define i32 @sub_const_const_sub(i32 %arg) {
; CHECK-LABEL: sub_const_const_sub:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #10
+; CHECK-NEXT: mov w8, #10 // =0xa
; CHECK-NEXT: sub w0, w8, w0
; CHECK-NEXT: ret
%t0 = sub i32 %arg, 8
@@ -414,7 +414,7 @@ define i32 @sub_const_const_sub_extrause(i32 %arg) {
; CHECK-NEXT: mov w19, w0
; CHECK-NEXT: sub w0, w0, #8
; CHECK-NEXT: bl use
-; CHECK-NEXT: mov w8, #10
+; CHECK-NEXT: mov w8, #10 // =0xa
; CHECK-NEXT: sub w0, w8, w19
; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: ret
@@ -475,7 +475,7 @@ define <4 x i32> @vec_sub_const_const_sub_nonsplat(<4 x i32> %arg) {
define i32 @const_sub_add_const(i32 %arg) {
; CHECK-LABEL: const_sub_add_const:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #10
+; CHECK-NEXT: mov w8, #10 // =0xa
; CHECK-NEXT: sub w0, w8, w0
; CHECK-NEXT: ret
%t0 = sub i32 8, %arg
@@ -490,11 +490,11 @@ define i32 @const_sub_add_const_extrause(i32 %arg) {
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w19, -8
; CHECK-NEXT: .cfi_offset w30, -16
-; CHECK-NEXT: mov w8, #8
+; CHECK-NEXT: mov w8, #8 // =0x8
; CHECK-NEXT: mov w19, w0
; CHECK-NEXT: sub w0, w8, w0
; CHECK-NEXT: bl use
-; CHECK-NEXT: mov w8, #10
+; CHECK-NEXT: mov w8, #10 // =0xa
; CHECK-NEXT: sub w0, w8, w19
; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: ret
@@ -555,7 +555,7 @@ define <4 x i32> @vec_const_sub_add_const_nonsplat(<4 x i32> %arg) {
define i32 @const_sub_sub_const(i32 %arg) {
; CHECK-LABEL: const_sub_sub_const:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #6
+; CHECK-NEXT: mov w8, #6 // =0x6
; CHECK-NEXT: sub w0, w8, w0
; CHECK-NEXT: ret
%t0 = sub i32 8, %arg
@@ -570,11 +570,11 @@ define i32 @const_sub_sub_const_extrause(i32 %arg) {
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w19, -8
; CHECK-NEXT: .cfi_offset w30, -16
-; CHECK-NEXT: mov w8, #8
+; CHECK-NEXT: mov w8, #8 // =0x8
; CHECK-NEXT: mov w19, w0
; CHECK-NEXT: sub w0, w8, w0
; CHECK-NEXT: bl use
-; CHECK-NEXT: mov w8, #6
+; CHECK-NEXT: mov w8, #6 // =0x6
; CHECK-NEXT: sub w0, w8, w19
; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: ret
@@ -649,11 +649,11 @@ define i32 @const_sub_const_sub_extrause(i32 %arg) {
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w19, -8
; CHECK-NEXT: .cfi_offset w30, -16
-; CHECK-NEXT: mov w8, #8
+; CHECK-NEXT: mov w8, #8 // =0x8
; CHECK-NEXT: sub w19, w8, w0
; CHECK-NEXT: mov w0, w19
; CHECK-NEXT: bl use
-; CHECK-NEXT: mov w8, #2
+; CHECK-NEXT: mov w8, #2 // =0x2
; CHECK-NEXT: sub w0, w8, w19
; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/sink-addsub-of-const.ll b/llvm/test/CodeGen/AArch64/sink-addsub-of-const.ll
index 0c1e61ff06401..1d5d2c2197bce 100644
--- a/llvm/test/CodeGen/AArch64/sink-addsub-of-const.ll
+++ b/llvm/test/CodeGen/AArch64/sink-addsub-of-const.ll
@@ -130,7 +130,7 @@ define i32 @sink_sub_from_const_to_sub(i32 %a, i32 %b) {
; CHECK-LABEL: sink_sub_from_const_to_sub:
; CHECK: // %bb.0:
; CHECK-NEXT: add w8, w0, w1
-; CHECK-NEXT: mov w9, #32
+; CHECK-NEXT: mov w9, #32 // =0x20
; CHECK-NEXT: sub w0, w9, w8
; CHECK-NEXT: ret
%t0 = sub i32 32, %a
diff --git a/llvm/test/CodeGen/AArch64/urem-seteq-illegal-types.ll b/llvm/test/CodeGen/AArch64/urem-seteq-illegal-types.ll
index e7f7e13756879..013feb67e380e 100644
--- a/llvm/test/CodeGen/AArch64/urem-seteq-illegal-types.ll
+++ b/llvm/test/CodeGen/AArch64/urem-seteq-illegal-types.ll
@@ -4,7 +4,7 @@
define i1 @test_urem_odd(i13 %X) nounwind {
; CHECK-LABEL: test_urem_odd:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #3277
+; CHECK-NEXT: mov w8, #3277 // =0xccd
; CHECK-NEXT: mul w8, w0, w8
; CHECK-NEXT: and w8, w8, #0x1fff
; CHECK-NEXT: cmp w8, #1639
@@ -18,13 +18,13 @@ define i1 @test_urem_odd(i13 %X) nounwind {
define i1 @test_urem_even(i27 %X) nounwind {
; CHECK-LABEL: test_urem_even:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #28087
+; CHECK-NEXT: mov w8, #28087 // =0x6db7
; CHECK-NEXT: movk w8, #1755, lsl #16
; CHECK-NEXT: mul w8, w0, w8
; CHECK-NEXT: lsl w9, w8, #26
; CHECK-NEXT: bfxil w9, w8, #1, #26
; CHECK-NEXT: and w8, w9, #0x7ffffff
-; CHECK-NEXT: mov w9, #18725
+; CHECK-NEXT: mov w9, #18725 // =0x4925
; CHECK-NEXT: movk w9, #146, lsl #16
; CHECK-NEXT: cmp w8, w9
; CHECK-NEXT: cset w0, lo
@@ -37,7 +37,7 @@ define i1 @test_urem_even(i27 %X) nounwind {
define i1 @test_urem_odd_setne(i4 %X) nounwind {
; CHECK-LABEL: test_urem_odd_setne:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #13
+; CHECK-NEXT: mov w8, #13 // =0xd
; CHECK-NEXT: mul w8, w0, w8
; CHECK-NEXT: and w8, w8, #0xf
; CHECK-NEXT: cmp w8, #3
@@ -51,7 +51,7 @@ define i1 @test_urem_odd_setne(i4 %X) nounwind {
define i1 @test_urem_negative_odd(i9 %X) nounwind {
; CHECK-LABEL: test_urem_negative_odd:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #307
+; CHECK-NEXT: mov w8, #307 // =0x133
; CHECK-NEXT: mul w8, w0, w8
; CHECK-NEXT: and w8, w8, #0x1ff
; CHECK-NEXT: cmp w8, #1
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