[PATCH] D152293: [RISCV] Use PACK in RISCVMatInt for constants that have the same lower and upper 32 bits.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: asb, luismarques, jrtc27, reames.
Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, hiraditya, arichardson.
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Herald added a project: LLVM.

This requires Zbkb.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D152293

Files:
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
  llvm/test/CodeGen/RISCV/rv64zbkb.ll


Index: llvm/test/CodeGen/RISCV/rv64zbkb.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rv64zbkb.ll
+++ llvm/test/CodeGen/RISCV/rv64zbkb.ll
@@ -290,3 +290,19 @@
   %8 = or i32 %6, %7
   ret i32 %8
 }
+
+define i64 @pack_i64_imm() {
+; RV64I-LABEL: pack_i64_imm:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    lui a0, %hi(.LCPI14_0)
+; RV64I-NEXT:    ld a0, %lo(.LCPI14_0)(a0)
+; RV64I-NEXT:    ret
+;
+; RV64ZBKB-LABEL: pack_i64_imm:
+; RV64ZBKB:       # %bb.0:
+; RV64ZBKB-NEXT:    lui a0, 65793
+; RV64ZBKB-NEXT:    addiw a0, a0, 16
+; RV64ZBKB-NEXT:    pack a0, a0, a0
+; RV64ZBKB-NEXT:    ret
+  ret i64 1157442765409226768 ; 0x0101010101010101
+}
Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
===================================================================
--- llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
+++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
@@ -242,6 +242,19 @@
     }
   }
 
+  // If the Low and High halves are the same, use PACK.
+  if (Res.size() > 2 && ActiveFeatures[RISCV::FeatureStdExtZbkb]) {
+    int64_t LoVal = SignExtend64<32>(Val);
+    int64_t HiVal = SignExtend64<32>(Val >> 32);
+    if (LoVal == HiVal) {
+      RISCVMatInt::InstSeq TmpSeq;
+      generateInstSeqImpl(LoVal, ActiveFeatures, TmpSeq);
+      TmpSeq.emplace_back(RISCV::PACK, 0);
+      if (TmpSeq.size() < Res.size())
+        Res = TmpSeq;
+    }
+  }
+
   // Perform optimization with BCLRI/BSETI in the Zbs extension.
   if (Res.size() > 2 && ActiveFeatures[RISCV::FeatureStdExtZbs]) {
     assert(ActiveFeatures[RISCV::Feature64Bit] &&
@@ -400,6 +413,7 @@
   case RISCV::SH1ADD:
   case RISCV::SH2ADD:
   case RISCV::SH3ADD:
+  case RISCV::PACK:
     return RISCVMatInt::RegReg;
   case RISCV::ADDI:
   case RISCV::ADDIW:


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