[PATCH] D152236: [RISCV] Add special case to selectImm for constants that can be created with (ADD (SLLI C, 32), C).

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:209
 
+  // See if we can create this constant as (ADDI (SLLI X, 32), X) where X is at
+  // worst an LUI+ADDIW. This will require an extra register, but avoids a
----------------
This should be ADD


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Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:225
+            0);
+        return SDValue(CurDAG->getMachineNode(RISCV::ADDI, DL, VT, Lo, SLLI),
+                       0);
----------------
craig.topper wrote:
> reames wrote:
> > If you swap these operands, does that help add immediate formation when the two halves are very small?
> > 
> > I'm thinking of the case 0x00020002.  This can be done as LI + SHL + ADDI.  With only a single register.  
> > 
> > This might not matter, and we might need a second special case for this, if so, feel free to punt to future patch.  
> > 
> > Thinking about, it's probably a subcase of having a general 32 bit constant hi, + a 12 bit low half which can always be done in 4 instructions, and 3 depending on the exact details of the high half.  
> This should be ADD not ADDI.
I assume you meant 0x0000000200000002? That should be handled by the base algorithm. https://godbolt.org/z/1rPsbh5a7

The base algorithm is basically subtract sign extended version of lo12 bits, count trailing zeros, shift right by that amount, recurse. The subtract becomes an ADDI and the shift right becomes a SLLI.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:4403
 
+  // Special case. See if we can build the constant as (ADDI (SLLI X, 32), X) do
+  // that if it will avoid a constant pool.
----------------
This should be ADD


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D152236/new/

https://reviews.llvm.org/D152236