[PATCH] D151997: [AMDGPU] Document amdgpu_cs_chain[_preserve] CCs. NFC
Jay Foad via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 6 01:33:25 PDT 2023
foad added inline comments.
================
Comment at: llvm/docs/AMDGPUUsage.rst:1111-1112
+ All counters (``lgkmcnt``, ``vmcnt``, ``storecnt``, etc.) are presumed in an
+ unknown state at function entry. Waits for regular memory counters are not
+ inserted as part of an ``llvm.amdgcn.cs.chain`` sequence in the function epilog.
+ However, we add waits for errata / hardware workarounds in the epilog:
----------------
I feel like this is missing some context. What is "an llvm.amdgcn.cs.chain sequence in the function epilog"???
================
Comment at: llvm/docs/AMDGPUUsage.rst:1113-1118
+ However, we add waits for errata / hardware workarounds in the epilog:
+
+ * On gfx11+, the function epilog waits for any scratch stores to be confirmed. This
+ works around the issue that we must wait for scratch stores before sending a
+ ``MSG_DEALLOC_VGPRS`` message.
+ * Additional waits may be required (e.g. ``s_waitcnt_depctr``).
----------------
I'm not sure any of this belongs in a calling convention description. The dealloc_vgprs thing applies to all kernels regardless of calling convention, but probably doesn't need to be documented to the end user anyway.
================
Comment at: llvm/docs/AMDGPUUsage.rst:1120-1121
+
+ Functions with this calling convention cannot be called directly. They must
+ instead be launched via the ``llvm.amdgcn.cs.chain`` intrinsic.
+
----------------
So they're not launched by hardware? That feels like the biggest difference from amdgpu_cs, and should probably be mentioned first.
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https://reviews.llvm.org/D151997
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