[llvm] 993a923 - [RISCV] Migrate to new encodeInstruction that uses SmallVectorImpl<char>. NFC
Fangrui Song via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 5 21:40:37 PDT 2023
Author: Fangrui Song
Date: 2023-06-05T21:40:32-07:00
New Revision: 993a923a09ec8ea4e895b4ea2331da99cc23d1a4
URL: https://github.com/llvm/llvm-project/commit/993a923a09ec8ea4e895b4ea2331da99cc23d1a4
DIFF: https://github.com/llvm/llvm-project/commit/993a923a09ec8ea4e895b4ea2331da99cc23d1a4.diff
LOG: [RISCV] Migrate to new encodeInstruction that uses SmallVectorImpl<char>. NFC
Similar to AArch64,AVR,PowerPC: 9e2d100e5322c52e29280c96bbb5609ca5af1539.
Added:
Modified:
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
index 9de4178e7bdef..b63a5cea823e4 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
@@ -49,19 +49,19 @@ class RISCVMCCodeEmitter : public MCCodeEmitter {
~RISCVMCCodeEmitter() override = default;
- void encodeInstruction(const MCInst &MI, raw_ostream &OS,
+ void encodeInstruction(const MCInst &MI, SmallVectorImpl<char> &CB,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const override;
- void expandFunctionCall(const MCInst &MI, raw_ostream &OS,
+ void expandFunctionCall(const MCInst &MI, SmallVectorImpl<char> &CB,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
- void expandAddTPRel(const MCInst &MI, raw_ostream &OS,
+ void expandAddTPRel(const MCInst &MI, SmallVectorImpl<char> &CB,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
- void expandLongCondBr(const MCInst &MI, raw_ostream &OS,
+ void expandLongCondBr(const MCInst &MI, SmallVectorImpl<char> &CB,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
@@ -108,7 +108,8 @@ MCCodeEmitter *llvm::createRISCVMCCodeEmitter(const MCInstrInfo &MCII,
// deal with it. When linker relaxation is enabled, AUIPC and JALR have a
// chance to relax to JAL.
// If the C extension is enabled, JAL has a chance relax to C_JAL.
-void RISCVMCCodeEmitter::expandFunctionCall(const MCInst &MI, raw_ostream &OS,
+void RISCVMCCodeEmitter::expandFunctionCall(const MCInst &MI,
+ SmallVectorImpl<char> &CB,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
MCInst TmpInst;
@@ -136,7 +137,7 @@ void RISCVMCCodeEmitter::expandFunctionCall(const MCInst &MI, raw_ostream &OS,
// Emit AUIPC Ra, Func with R_RISCV_CALL relocation type.
TmpInst = MCInstBuilder(RISCV::AUIPC).addReg(Ra).addExpr(CallExpr);
Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
- support::endian::write(OS, Binary, support::little);
+ support::endian::write(CB, Binary, support::little);
if (MI.getOpcode() == RISCV::PseudoTAIL ||
MI.getOpcode() == RISCV::PseudoJump)
@@ -146,11 +147,12 @@ void RISCVMCCodeEmitter::expandFunctionCall(const MCInst &MI, raw_ostream &OS,
// Emit JALR Ra, Ra, 0
TmpInst = MCInstBuilder(RISCV::JALR).addReg(Ra).addReg(Ra).addImm(0);
Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
- support::endian::write(OS, Binary, support::little);
+ support::endian::write(CB, Binary, support::little);
}
// Expand PseudoAddTPRel to a simple ADD with the correct relocation.
-void RISCVMCCodeEmitter::expandAddTPRel(const MCInst &MI, raw_ostream &OS,
+void RISCVMCCodeEmitter::expandAddTPRel(const MCInst &MI,
+ SmallVectorImpl<char> &CB,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
MCOperand DestReg = MI.getOperand(0);
@@ -184,7 +186,7 @@ void RISCVMCCodeEmitter::expandAddTPRel(const MCInst &MI, raw_ostream &OS,
.addOperand(SrcReg)
.addOperand(TPReg);
uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
- support::endian::write(OS, Binary, support::little);
+ support::endian::write(CB, Binary, support::little);
}
static unsigned getInvertedBranchOp(unsigned BrOp) {
@@ -208,7 +210,8 @@ static unsigned getInvertedBranchOp(unsigned BrOp) {
// Expand PseudoLongBxx to an inverted conditional branch and an unconditional
// jump.
-void RISCVMCCodeEmitter::expandLongCondBr(const MCInst &MI, raw_ostream &OS,
+void RISCVMCCodeEmitter::expandLongCondBr(const MCInst &MI,
+ SmallVectorImpl<char> &CB,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
MCRegister SrcReg1 = MI.getOperand(0).getReg();
@@ -237,14 +240,14 @@ void RISCVMCCodeEmitter::expandLongCondBr(const MCInst &MI, raw_ostream &OS,
Opcode == RISCV::PseudoLongBNE ? RISCV::C_BEQZ : RISCV::C_BNEZ;
MCInst TmpInst = MCInstBuilder(InvOpc).addReg(SrcReg1).addImm(6);
uint16_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
- support::endian::write<uint16_t>(OS, Binary, support::little);
+ support::endian::write<uint16_t>(CB, Binary, support::little);
Offset = 2;
} else {
unsigned InvOpc = getInvertedBranchOp(Opcode);
MCInst TmpInst =
MCInstBuilder(InvOpc).addReg(SrcReg1).addReg(SrcReg2).addImm(8);
uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
- support::endian::write(OS, Binary, support::little);
+ support::endian::write(CB, Binary, support::little);
Offset = 4;
}
@@ -252,7 +255,7 @@ void RISCVMCCodeEmitter::expandLongCondBr(const MCInst &MI, raw_ostream &OS,
MCInst TmpInst =
MCInstBuilder(RISCV::JAL).addReg(RISCV::X0).addOperand(SrcSymbol);
uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
- support::endian::write(OS, Binary, support::little);
+ support::endian::write(CB, Binary, support::little);
Fixups.clear();
if (SrcSymbol.isExpr()) {
@@ -262,7 +265,8 @@ void RISCVMCCodeEmitter::expandLongCondBr(const MCInst &MI, raw_ostream &OS,
}
}
-void RISCVMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
+void RISCVMCCodeEmitter::encodeInstruction(const MCInst &MI,
+ SmallVectorImpl<char> &CB,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
@@ -279,11 +283,11 @@ void RISCVMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
case RISCV::PseudoCALL:
case RISCV::PseudoTAIL:
case RISCV::PseudoJump:
- expandFunctionCall(MI, OS, Fixups, STI);
+ expandFunctionCall(MI, CB, Fixups, STI);
MCNumEmitted += 2;
return;
case RISCV::PseudoAddTPRel:
- expandAddTPRel(MI, OS, Fixups, STI);
+ expandAddTPRel(MI, CB, Fixups, STI);
MCNumEmitted += 1;
return;
case RISCV::PseudoLongBEQ:
@@ -292,7 +296,7 @@ void RISCVMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
case RISCV::PseudoLongBGE:
case RISCV::PseudoLongBLTU:
case RISCV::PseudoLongBGEU:
- expandLongCondBr(MI, OS, Fixups, STI);
+ expandLongCondBr(MI, CB, Fixups, STI);
MCNumEmitted += 2;
return;
}
@@ -302,12 +306,12 @@ void RISCVMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
llvm_unreachable("Unhandled encodeInstruction length!");
case 2: {
uint16_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
- support::endian::write<uint16_t>(OS, Bits, support::little);
+ support::endian::write<uint16_t>(CB, Bits, support::little);
break;
}
case 4: {
uint32_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
- support::endian::write(OS, Bits, support::little);
+ support::endian::write(CB, Bits, support::little);
break;
}
}
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