[llvm] 77da27b - [RISCV] Improve selection for vector fpclass.
Jianjian GUAN via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 5 19:24:33 PDT 2023
Author: Jianjian GUAN
Date: 2023-06-06T10:24:24+08:00
New Revision: 77da27b5e36ce74ad584da331b568d6d757343a8
URL: https://github.com/llvm/llvm-project/commit/77da27b5e36ce74ad584da331b568d6d757343a8
DIFF: https://github.com/llvm/llvm-project/commit/77da27b5e36ce74ad584da331b568d6d757343a8.diff
LOG: [RISCV] Improve selection for vector fpclass.
Since vfclass intruction will only set one single bit in the result, so if we only want to check 1 fp class, we could use vmseq to do it.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D151967
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfclass.ll
llvm/test/CodeGen/RISCV/rvv/vfclass-sdnode.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index abefb8d152d3c..99a0d4d7a90c6 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -4462,6 +4462,8 @@ SDValue RISCVTargetLowering::LowerIS_FPCLASS(SDValue Op,
if (Check & fcNegZero)
TDCMask |= RISCV::FPMASK_Negative_Zero;
+ bool IsOneBitMask = isPowerOf2_32(TDCMask);
+
SDValue TDCMaskV = DAG.getConstant(TDCMask, DL, XLenVT);
if (VT.isVector()) {
@@ -4473,6 +4475,10 @@ SDValue RISCVTargetLowering::LowerIS_FPCLASS(SDValue Op,
auto [Mask, VL] = getDefaultScalableVLOps(VT0, DL, DAG, Subtarget);
SDValue FPCLASS = DAG.getNode(RISCVISD::FCLASS_VL, DL, DstVT, Op0, Mask,
VL, Op->getFlags());
+ if (IsOneBitMask)
+ return DAG.getSetCC(DL, VT, FPCLASS,
+ DAG.getConstant(TDCMask, DL, DstVT),
+ ISD::CondCode::SETEQ);
SDValue AND = DAG.getNode(ISD::AND, DL, DstVT, FPCLASS,
DAG.getConstant(TDCMask, DL, DstVT));
return DAG.getSetCC(DL, VT, AND, DAG.getConstant(0, DL, DstVT),
@@ -4491,6 +4497,13 @@ SDValue RISCVTargetLowering::LowerIS_FPCLASS(SDValue Op,
TDCMaskV = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, ContainerDstVT,
DAG.getUNDEF(ContainerDstVT), TDCMaskV, VL);
+ if (IsOneBitMask) {
+ SDValue VMSEQ =
+ DAG.getNode(RISCVISD::SETCC_VL, DL, ContainerVT,
+ {FPCLASS, TDCMaskV, DAG.getCondCode(ISD::SETEQ),
+ DAG.getUNDEF(ContainerVT), Mask, VL});
+ return convertFromScalableVector(VT, VMSEQ, DAG, Subtarget);
+ }
SDValue AND = DAG.getNode(RISCVISD::AND_VL, DL, ContainerDstVT, FPCLASS,
TDCMaskV, DAG.getUNDEF(ContainerDstVT), Mask, VL);
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfclass.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfclass.ll
index f507db7fe4f4d..3fc8aadbf28cd 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfclass.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfclass.ll
@@ -50,8 +50,7 @@ define <8 x i1> @isnan_v8f32(<8 x float> %x) {
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfclass.v v8, v8
; CHECK-NEXT: li a0, 512
-; CHECK-NEXT: vand.vx v8, v8, a0
-; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: vmseq.vx v0, v8, a0
; CHECK-NEXT: ret
%1 = call <8 x i1> @llvm.is.fpclass.v8f32(<8 x float> %x, i32 2)
ret <8 x i1> %1
@@ -63,8 +62,7 @@ define <16 x i1> @isnan_v16f32(<16 x float> %x) {
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vfclass.v v8, v8
; CHECK-NEXT: li a0, 256
-; CHECK-NEXT: vand.vx v8, v8, a0
-; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: vmseq.vx v0, v8, a0
; CHECK-NEXT: ret
%1 = call <16 x i1> @llvm.is.fpclass.v16f32(<16 x float> %x, i32 1)
ret <16 x i1> %1
@@ -89,8 +87,7 @@ define <4 x i1> @isposinf_v4f64(<4 x double> %x) {
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vfclass.v v8, v8
; CHECK-NEXT: li a0, 128
-; CHECK-NEXT: vand.vx v8, v8, a0
-; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: vmseq.vx v0, v8, a0
; CHECK-NEXT: ret
%1 = call <4 x i1> @llvm.is.fpclass.v4f64(<4 x double> %x, i32 512) ; 0x200 = "+inf"
ret <4 x i1> %1
@@ -101,8 +98,7 @@ define <8 x i1> @isneginf_v8f64(<8 x double> %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-NEXT: vfclass.v v8, v8
-; CHECK-NEXT: vand.vi v8, v8, 1
-; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: vmseq.vi v0, v8, 1
; CHECK-NEXT: ret
%1 = call <8 x i1> @llvm.is.fpclass.v8f64(<8 x double> %x, i32 4) ; "-inf"
ret <8 x i1> %1
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfclass-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfclass-sdnode.ll
index d0fc44a9e68c4..3f054f83d3d38 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfclass-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfclass-sdnode.ll
@@ -50,8 +50,7 @@ define <vscale x 8 x i1> @isnan_nxv8f32(<vscale x 8 x float> %x) {
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vfclass.v v8, v8
; CHECK-NEXT: li a0, 512
-; CHECK-NEXT: vand.vx v8, v8, a0
-; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: vmseq.vx v0, v8, a0
; CHECK-NEXT: ret
%1 = call <vscale x 8 x i1> @llvm.is.fpclass.nxv8f32(<vscale x 8 x float> %x, i32 2)
ret <vscale x 8 x i1> %1
@@ -63,8 +62,7 @@ define <vscale x 16 x i1> @isnan_nxv16f32(<vscale x 16 x float> %x) {
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; CHECK-NEXT: vfclass.v v8, v8
; CHECK-NEXT: li a0, 256
-; CHECK-NEXT: vand.vx v8, v8, a0
-; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: vmseq.vx v0, v8, a0
; CHECK-NEXT: ret
%1 = call <vscale x 16 x i1> @llvm.is.fpclass.nxv16f32(<vscale x 16 x float> %x, i32 1)
ret <vscale x 16 x i1> %1
@@ -89,8 +87,7 @@ define <vscale x 4 x i1> @isposinf_nxv4f64(<vscale x 4 x double> %x) {
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; CHECK-NEXT: vfclass.v v8, v8
; CHECK-NEXT: li a0, 128
-; CHECK-NEXT: vand.vx v8, v8, a0
-; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: vmseq.vx v0, v8, a0
; CHECK-NEXT: ret
%1 = call <vscale x 4 x i1> @llvm.is.fpclass.nxv4f64(<vscale x 4 x double> %x, i32 512) ; 0x200 = "+inf"
ret <vscale x 4 x i1> %1
@@ -101,8 +98,7 @@ define <vscale x 8 x i1> @isneginf_nxv8f64(<vscale x 8 x double> %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-NEXT: vfclass.v v8, v8
-; CHECK-NEXT: vand.vi v8, v8, 1
-; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: vmseq.vi v0, v8, 1
; CHECK-NEXT: ret
%1 = call <vscale x 8 x i1> @llvm.is.fpclass.nxv8f64(<vscale x 8 x double> %x, i32 4) ; "-inf"
ret <vscale x 8 x i1> %1
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