[PATCH] D152161: [AArch64][NFC] Normalise name of indexed forms of SQRDMLAH/SQRDMLSH
Ricardo Jesus via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 5 06:50:01 PDT 2023
rjj created this revision.
rjj added reviewers: dmgreen, SjoerdMeijer.
Herald added subscribers: arphaman, hiraditya, kristof.beyls.
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rjj requested review of this revision.
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Herald added a subscriber: llvm-commits.
Most indexed vector instructions are suffixed with v<N><TY>_indexed.
SQRDMLAH/SQRDMLSH are the exception—they are suffixed with <TY>_indexed.
This can complicate matching slightly.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D152161
Files:
llvm/lib/Target/AArch64/AArch64InstrFormats.td
Index: llvm/lib/Target/AArch64/AArch64InstrFormats.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -10862,19 +10862,19 @@
let Inst{21} = idx{0};
}
- def i16_indexed : BaseSIMDIndexedTied<1, U, 1, 0b01, opc,
- FPR16Op, FPR16Op, V128_lo,
- VectorIndexH, asm, ".h", "", "", ".h",
- []> {
+ def v1i16_indexed : BaseSIMDIndexedTied<1, U, 1, 0b01, opc,
+ FPR16Op, FPR16Op, V128_lo,
+ VectorIndexH, asm, ".h", "", "", ".h",
+ []> {
bits<3> idx;
let Inst{11} = idx{2};
let Inst{21} = idx{1};
let Inst{20} = idx{0};
}
- def i32_indexed : BaseSIMDIndexedTied<1, U, 1, 0b10, opc,
- FPR32Op, FPR32Op, V128, VectorIndexS,
- asm, ".s", "", "", ".s",
+ def v1i32_indexed : BaseSIMDIndexedTied<1, U, 1, 0b10, opc,
+ FPR32Op, FPR32Op, V128, VectorIndexS,
+ asm, ".s", "", "", ".s",
[(set (i32 FPR32Op:$dst),
(i32 (op (i32 FPR32Op:$Rd), (i32 FPR32Op:$Rn),
(i32 (vector_extract (v4i32 V128:$Rm),
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