[llvm] d37bd54 - [X86] canonicalizeShuffleWithBinOps - ensure a binary shuffle of binops have the same value type

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2023-06-05T11:18:28+01:00
New Revision: d37bd544ffe0e56abd4554493b278ecc64e3d51a

URL: https://github.com/llvm/llvm-project/commit/d37bd544ffe0e56abd4554493b278ecc64e3d51a
DIFF: https://github.com/llvm/llvm-project/commit/d37bd544ffe0e56abd4554493b278ecc64e3d51a.diff

LOG: [X86] canonicalizeShuffleWithBinOps - ensure a binary shuffle of binops have the same value type

Fixes #63091

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp
    llvm/test/CodeGen/X86/pr63091.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index f660c84c9167d..2542c8d1a3c63 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -41808,6 +41808,7 @@ static SDValue canonicalizeShuffleWithBinOps(SDValue N, SelectionDAG &DAG,
       SDValue N1 = peekThroughOneUseBitcasts(N.getOperand(1));
       unsigned SrcOpcode = N0.getOpcode();
       if (TLI.isBinOp(SrcOpcode) && N1.getOpcode() == SrcOpcode &&
+          N0.getValueType() == N1.getValueType() &&
           IsSafeToMoveShuffle(N0, SrcOpcode) &&
           IsSafeToMoveShuffle(N1, SrcOpcode)) {
         SDValue Op00 = peekThroughOneUseBitcasts(N0.getOperand(0));

diff  --git a/llvm/test/CodeGen/X86/pr63091.ll b/llvm/test/CodeGen/X86/pr63091.ll
index 2982e3a755e9b..3f50be8ab8df9 100644
--- a/llvm/test/CodeGen/X86/pr63091.ll
+++ b/llvm/test/CodeGen/X86/pr63091.ll
@@ -5,20 +5,22 @@
 
 ; Ensure canonicalizeShuffleWithBinOps doesn't merge binops with 
diff erent types
 
-; FIXME: Don't merge PCMPGT nodes of 
diff erent types
+; Don't merge PCMPGT nodes of 
diff erent types
 define <4 x i32> @dont_merge_pcmpgt(<16 x i8> %0, <4 x i32> %1) {
 ; SSE-LABEL: dont_merge_pcmpgt:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    pxor %xmm2, %xmm2
-; SSE-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5],xmm1[6,7]
 ; SSE-NEXT:    pcmpgtb %xmm2, %xmm0
+; SSE-NEXT:    pcmpgtd %xmm2, %xmm1
+; SSE-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5],xmm1[6,7]
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: dont_merge_pcmpgt:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vpxor %xmm2, %xmm2, %xmm2
-; AVX-NEXT:    vpblendd {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[3]
 ; AVX-NEXT:    vpcmpgtb %xmm2, %xmm0, %xmm0
+; AVX-NEXT:    vpcmpgtd %xmm2, %xmm1, %xmm1
+; AVX-NEXT:    vpblendd {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[3]
 ; AVX-NEXT:    retq
   %3 = icmp sgt <16 x i8> %0, zeroinitializer
   %4 = sext <16 x i1> %3 to <16 x i8>