[llvm] 3030c03 - [AMDGPU] Make use of MachineInstr::all_defs and all_uses. NFCI.
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 5 02:32:40 PDT 2023
Author: Jay Foad
Date: 2023-06-05T10:32:33+01:00
New Revision: 3030c03988c5f5a4fb1f8bee6a156367b28b0268
URL: https://github.com/llvm/llvm-project/commit/3030c03988c5f5a4fb1f8bee6a156367b28b0268
DIFF: https://github.com/llvm/llvm-project/commit/3030c03988c5f5a4fb1f8bee6a156367b28b0268.diff
LOG: [AMDGPU] Make use of MachineInstr::all_defs and all_uses. NFCI.
Added:
Modified:
llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
llvm/lib/Target/AMDGPU/GCNIterativeScheduler.cpp
llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
llvm/lib/Target/AMDGPU/SIOptimizeVGPRLiveRange.cpp
llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
index 5ae5cedec40e8..fe0ae3b298b44 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -850,10 +850,7 @@ bool AMDGPURegisterBankInfo::executeInWaterfallLoop(
assert(std::distance(NewBegin, NewEnd) == OrigRangeSize);
for (MachineInstr &MI : make_range(NewBegin, NewEnd)) {
- for (MachineOperand &Op : MI.uses()) {
- if (!Op.isReg() || Op.isDef())
- continue;
-
+ for (MachineOperand &Op : MI.all_uses()) {
Register OldReg = Op.getReg();
if (!SGPROperandRegs.count(OldReg))
continue;
diff --git a/llvm/lib/Target/AMDGPU/GCNIterativeScheduler.cpp b/llvm/lib/Target/AMDGPU/GCNIterativeScheduler.cpp
index 77960ef62f3a7..d89c9b1febded 100644
--- a/llvm/lib/Target/AMDGPU/GCNIterativeScheduler.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNIterativeScheduler.cpp
@@ -367,9 +367,8 @@ void GCNIterativeScheduler::scheduleRegion(Region &R, Range &&Schedule,
}
if (!MI->isDebugInstr()) {
// Reset read - undef flags and update them later.
- for (auto &Op : MI->operands())
- if (Op.isReg() && Op.isDef())
- Op.setIsUndef(false);
+ for (auto &Op : MI->all_defs())
+ Op.setIsUndef(false);
RegisterOperands RegOpers;
RegOpers.collect(*MI, *TRI, MRI, /*ShouldTrackLaneMasks*/true,
diff --git a/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp b/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
index 4b055d883e389..68cf971703692 100644
--- a/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
@@ -286,8 +286,8 @@ void GCNUpwardRPTracker::recede(const MachineInstr &MI) {
// update max pressure
MaxPressure = max(AtMIPressure, MaxPressure);
- for (const auto &MO : MI.operands()) {
- if (!MO.isReg() || !MO.isDef() || !MO.getReg().isVirtual() || MO.isDead())
+ for (const auto &MO : MI.all_defs()) {
+ if (!MO.getReg().isVirtual() || MO.isDead())
continue;
auto Reg = MO.getReg();
@@ -382,9 +382,7 @@ void GCNDownwardRPTracker::advanceToNext() {
NextMI = skipDebugInstructionsForward(NextMI, MBBEnd);
// Add new registers or mask bits.
- for (const auto &MO : LastTrackedMI->operands()) {
- if (!MO.isReg() || !MO.isDef())
- continue;
+ for (const auto &MO : LastTrackedMI->all_defs()) {
Register Reg = MO.getReg();
if (!Reg.isVirtual())
continue;
diff --git a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
index 32fd64f1140dd..5bf47d145ebe6 100644
--- a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
@@ -1201,9 +1201,8 @@ void GCNSchedStage::revertScheduling() {
}
// Reset read-undef flags and update them later.
- for (auto &Op : MI->operands())
- if (Op.isReg() && Op.isDef())
- Op.setIsUndef(false);
+ for (auto &Op : MI->all_defs())
+ Op.setIsUndef(false);
RegisterOperands RegOpers;
RegOpers.collect(*MI, *DAG.TRI, DAG.MRI, DAG.ShouldTrackLaneMasks, false);
if (!MI->isDebugInstr()) {
@@ -1476,8 +1475,8 @@ bool PreRARematStage::isTriviallyReMaterializable(const MachineInstr &MI) {
if (!DAG.TII->isTriviallyReMaterializable(MI))
return false;
- for (const MachineOperand &MO : MI.operands())
- if (MO.isReg() && MO.isUse() && MO.getReg().isVirtual())
+ for (const MachineOperand &MO : MI.all_uses())
+ if (MO.getReg().isVirtual())
return false;
return true;
diff --git a/llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp b/llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp
index a1eb8150595f2..edcfd994033e7 100644
--- a/llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp
@@ -119,9 +119,7 @@ static bool isValidClauseInst(const MachineInstr &MI, bool IsVMEMClause) {
// If this is a load instruction where the result has been coalesced with an operand, then we cannot clause it.
for (const MachineOperand &ResMO : MI.defs()) {
Register ResReg = ResMO.getReg();
- for (const MachineOperand &MO : MI.uses()) {
- if (!MO.isReg() || MO.isDef())
- continue;
+ for (const MachineOperand &MO : MI.all_uses()) {
if (MO.getReg() == ResReg)
return false;
}
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 2c3f0ebae21cc..399b18ec35ca0 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -5793,11 +5793,8 @@ loadMBUFScalarOperandsFromVGPR(const SIInstrInfo &TII, MachineInstr &MI,
MachineBasicBlock::iterator AfterMI = MI;
++AfterMI;
for (auto I = Begin; I != AfterMI; I++) {
- for (auto &MO : I->uses()) {
- if (MO.isReg() && MO.isUse()) {
- MRI.clearKillFlags(MO.getReg());
- }
- }
+ for (auto &MO : I->all_uses())
+ MRI.clearKillFlags(MO.getReg());
}
// To insert the loop we need to split the block. Move everything after this
diff --git a/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp b/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
index 9607092c70afe..00cb5b2878f41 100644
--- a/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
+++ b/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
@@ -524,8 +524,8 @@ MachineBasicBlock *SILowerControlFlow::emitEndCf(MachineInstr &MI) {
for (MachineBasicBlock *BlockPiece : {&MBB, SplitBB}) {
for (MachineInstr &X : *BlockPiece) {
- for (MachineOperand &Op : X.operands()) {
- if (Op.isReg() && Op.isDef() && Op.getReg().isVirtual())
+ for (MachineOperand &Op : X.all_defs()) {
+ if (Op.getReg().isVirtual())
DefInOrigBlock.insert(Op.getReg());
}
}
diff --git a/llvm/lib/Target/AMDGPU/SIOptimizeVGPRLiveRange.cpp b/llvm/lib/Target/AMDGPU/SIOptimizeVGPRLiveRange.cpp
index 126f56100c64a..e95abae88d7a8 100644
--- a/llvm/lib/Target/AMDGPU/SIOptimizeVGPRLiveRange.cpp
+++ b/llvm/lib/Target/AMDGPU/SIOptimizeVGPRLiveRange.cpp
@@ -357,8 +357,8 @@ void SIOptimizeVGPRLiveRange::collectWaterfallCandidateRegisters(
for (auto *I : Instructions) {
auto &MI = *I;
- for (auto &MO : MI.operands()) {
- if (!MO.isReg() || !MO.getReg() || MO.isDef())
+ for (auto &MO : MI.all_uses()) {
+ if (!MO.getReg())
continue;
Register MOReg = MO.getReg();
diff --git a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
index 7b5f91e922d8e..a0500cbd4cd39 100644
--- a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
+++ b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
@@ -381,8 +381,8 @@ void SIWholeQuadMode::markDefs(const MachineInstr &UseMI, LiveRange &LR,
if (Reg.isVirtual()) {
// Iterate over all operands to find relevant definitions
bool HasDef = false;
- for (const MachineOperand &Op : MI->operands()) {
- if (!(Op.isReg() && Op.isDef() && Op.getReg() == Reg))
+ for (const MachineOperand &Op : MI->all_defs()) {
+ if (Op.getReg() != Reg)
continue;
// Compute lanes defined and overlap with use
@@ -472,11 +472,8 @@ void SIWholeQuadMode::markInstructionUses(const MachineInstr &MI, char Flag,
LLVM_DEBUG(dbgs() << "markInstructionUses " << PrintState(Flag) << ": "
<< MI);
- for (const MachineOperand &Use : MI.uses()) {
- if (!Use.isReg() || !Use.isUse())
- continue;
+ for (const MachineOperand &Use : MI.all_uses())
markOperand(MI, Use, Flag, Worklist);
- }
}
// Scan instructions to determine which ones require an Exact execmask and
@@ -1186,11 +1183,9 @@ MachineBasicBlock::iterator SIWholeQuadMode::prepareInsertion(
// does not need to be preserved.
while (MBBI != Last) {
bool IsExecDef = false;
- for (const MachineOperand &MO : MBBI->operands()) {
- if (MO.isReg() && MO.isDef()) {
- IsExecDef |=
- MO.getReg() == AMDGPU::EXEC_LO || MO.getReg() == AMDGPU::EXEC;
- }
+ for (const MachineOperand &MO : MBBI->all_defs()) {
+ IsExecDef |=
+ MO.getReg() == AMDGPU::EXEC_LO || MO.getReg() == AMDGPU::EXEC;
}
if (!IsExecDef)
break;
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