[PATCH] D152128: [RISCV] Fold special case (xor (setcc constant, y, setlt), 1) -> (setcc y, constant + 1, setlt)

[Liao Chunyu via Phabricator via llvm-commits]

liaolucy updated this revision to Diff 528328.
liaolucy added a comment.

[RISCV]Fold xor(setcc x, y, cond), 1 --> setcc (x, y, inverted(cond))


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D152128/new/

https://reviews.llvm.org/D152128

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/double-br-fcmp.ll
  llvm/test/CodeGen/RISCV/double-convert.ll
  llvm/test/CodeGen/RISCV/double-fcmp.ll
  llvm/test/CodeGen/RISCV/double-previous-failure.ll
  llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
  llvm/test/CodeGen/RISCV/double-select-fcmp.ll
  llvm/test/CodeGen/RISCV/double-select-icmp.ll
  llvm/test/CodeGen/RISCV/float-br-fcmp.ll
  llvm/test/CodeGen/RISCV/float-convert.ll
  llvm/test/CodeGen/RISCV/float-fcmp.ll
  llvm/test/CodeGen/RISCV/float-round-conv-sat.ll
  llvm/test/CodeGen/RISCV/float-select-fcmp.ll
  llvm/test/CodeGen/RISCV/float-select-icmp.ll
  llvm/test/CodeGen/RISCV/half-br-fcmp.ll
  llvm/test/CodeGen/RISCV/half-convert.ll
  llvm/test/CodeGen/RISCV/half-fcmp.ll
  llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
  llvm/test/CodeGen/RISCV/half-select-fcmp.ll
  llvm/test/CodeGen/RISCV/half-select-icmp.ll
  llvm/test/CodeGen/RISCV/zbb-cmp-combine.ll

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