[PATCH] D152130: [AVR] Optimize 8-bit rotation

[Ben Shi via Phabricator via llvm-commits]

benshi001 updated this revision to Diff 528317.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D152130/new/

https://reviews.llvm.org/D152130

Files:
  llvm/lib/Target/AVR/AVRISelLowering.cpp
  llvm/test/CodeGen/AVR/rotate.ll


Index: llvm/test/CodeGen/AVR/rotate.ll
===================================================================
--- llvm/test/CodeGen/AVR/rotate.ll
+++ llvm/test/CodeGen/AVR/rotate.ll
@@ -30,14 +30,7 @@
 define i8 @rotl8_5(i8 %x) {
 ; CHECK-LABEL: rotl8_5:
 ; CHECK:       ; %bb.0: ; %start
-; CHECK-NEXT:    lsl r24
-; CHECK-NEXT:    adc r24, r1
-; CHECK-NEXT:    lsl r24
-; CHECK-NEXT:    adc r24, r1
-; CHECK-NEXT:    lsl r24
-; CHECK-NEXT:    adc r24, r1
-; CHECK-NEXT:    lsl r24
-; CHECK-NEXT:    adc r24, r1
+; CHECK-NEXT:    swap r24
 ; CHECK-NEXT:    lsl r24
 ; CHECK-NEXT:    adc r24, r1
 ; CHECK-NEXT:    ret
@@ -98,18 +91,7 @@
 define i8 @rotr8_5(i8 %x) {
 ; CHECK-LABEL: rotr8_5:
 ; CHECK:       ; %bb.0: ; %start
-; CHECK-NEXT:    bst r24, 0
-; CHECK-NEXT:    ror r24
-; CHECK-NEXT:    bld r24, 7
-; CHECK-NEXT:    bst r24, 0
-; CHECK-NEXT:    ror r24
-; CHECK-NEXT:    bld r24, 7
-; CHECK-NEXT:    bst r24, 0
-; CHECK-NEXT:    ror r24
-; CHECK-NEXT:    bld r24, 7
-; CHECK-NEXT:    bst r24, 0
-; CHECK-NEXT:    ror r24
-; CHECK-NEXT:    bld r24, 7
+; CHECK-NEXT:    swap r24
 ; CHECK-NEXT:    bst r24, 0
 ; CHECK-NEXT:    ror r24
 ; CHECK-NEXT:    bld r24, 7
Index: llvm/lib/Target/AVR/AVRISelLowering.cpp
===================================================================
--- llvm/lib/Target/AVR/AVRISelLowering.cpp
+++ llvm/lib/Target/AVR/AVRISelLowering.cpp
@@ -427,6 +427,10 @@
       Victim = DAG.getNode(AVRISD::ASRBN, dl, VT, Victim,
                            DAG.getConstant(7, dl, VT));
       ShiftAmount = 0;
+    } else if ((Op.getOpcode() == ISD::ROTL || Op.getOpcode() == ISD::ROTR)
+               && ShiftAmount >= 4) {
+      Victim = DAG.getNode(AVRISD::SWAP, dl, VT, Victim);
+      ShiftAmount -= 4;
     }
   } else if (VT.getSizeInBits() == 16) {
     if (Op.getOpcode() == ISD::SRA)


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