[PATCH] D134599: [RISCV] Readjusting the framestack for Zcmp

[Yeting Kuo via Phabricator via llvm-commits]

fakepaper56 added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:1334
+    }
+  } else {
+    const char *SpillLibCall = getSpillLibCallName(*MF, CSI);
----------------
you could use `else if (const char *SpillLibCall = getSpillLibCallName(*MF, CSI))` here.


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Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:1377
+    }
+    RVFI->setRVPushStackSize(PoshPopRegs * (IsRV64 ? 8 : 4));
+
----------------
VincentWu wrote:
> fakepaper56 wrote:
> > IMHO, is it possible the callee save register needed spilled are not successive, like {ra, s0, s3}? 
> I think it should not support this syntax.
> In spec, it is valid only in the following cases:
> 
> {F27468105}
My idea is your code may raise problem when we need to spill s3 but not spill s1 and s2. The stack size you calculated is register number is 3 but indeed you spill 5 register.


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  https://reviews.llvm.org/D134599/new/

https://reviews.llvm.org/D134599