[PATCH] D150941: [LegalizeType][X86] Support WidenVecRes_AssertZext and SplitVecRes_AssertZext for ISD::AssertZext during LegalizeType procedure

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp:575
+void DAGTypeLegalizer::SplitVecRes_AssertZext(SDNode *N, SDValue &Lo,
+                                           SDValue &Hi) {
+  SDValue L, H;
----------------
This isn't indented enough


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Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:951
   case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
+  case ISD::AssertZext:    SplitVecRes_AssertZext(N, Lo, Hi); break;
   case ISD::VSELECT:
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Line up with the previous line.


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Comment at: llvm/test/CodeGen/X86/legalize-vec-assertzext.ll:14
+; CHECK-NEXT:    retq
+    %e = call <16 x i64> @test(), !range !0
+    %d = extractelement <16 x i64> %e, i32 15
----------------
Doesn't IR normally use 2 spaces of indentation not 4?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D150941/new/

https://reviews.llvm.org/D150941