[llvm] 5ba10ad - [NFC][RISCV] Replace global def containing only one field with defvar

[via llvm-commits]

Author: wangpc
Date: 2023-05-22T10:47:32+08:00
New Revision: 5ba10ad9dc43a0c5dc2883ae6fac64307f689820

URL: https://github.com/llvm/llvm-project/commit/5ba10ad9dc43a0c5dc2883ae6fac64307f689820
DIFF: https://github.com/llvm/llvm-project/commit/5ba10ad9dc43a0c5dc2883ae6fac64307f689820.diff

LOG: [NFC][RISCV] Replace global def containing only one field with defvar

This simplifies some code.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D150935

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVRegisterInfo.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
index a27a50cb80100..120b9191cc58b 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -342,9 +342,7 @@ defvar vbool32_t = nxv2i1;
 defvar vbool64_t = nxv1i1;
 
 // There is no need to define register classes for fractional LMUL.
-def LMULList {
-  list<int> m = [1, 2, 4, 8];
-}
+defvar LMULList = [1, 2, 4, 8];
 
 //===----------------------------------------------------------------------===//
 // Utility classes for segment load/store.
@@ -576,7 +574,7 @@ def VM : VReg<VMaskVTs,
            (add (sequence "V%u", 8, 31),
                 (sequence "V%u", 0, 7)), 1>;
 
-foreach m = LMULList.m in {
+foreach m = LMULList in {
   foreach nf = NFList<m>.L in {
     def "VRN" # nf # "M" # m # "NoV0": VReg<[untyped],
                                (add !cast<RegisterTuples>("VN" # nf # "M" # m # "NoV0")),