[llvm] f603809 - [X86] Move encoding optimization for PUSH32i, PUSH64i to MC lowering, NFCI
Shengchen Kan via llvm-commits
llvm-commits at lists.llvm.org
Sat May 20 02:59:57 PDT 2023
Author: Shengchen Kan
Date: 2023-05-20T17:59:43+08:00
New Revision: f6038096378e2d9870b1f29fb3a2ce442df88778
URL: https://github.com/llvm/llvm-project/commit/f6038096378e2d9870b1f29fb3a2ce442df88778
DIFF: https://github.com/llvm/llvm-project/commit/f6038096378e2d9870b1f29fb3a2ce442df88778.diff
LOG: [X86] Move encoding optimization for PUSH32i, PUSH64i to MC lowering, NFCI
Added:
Modified:
llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.cpp
llvm/lib/Target/X86/X86CallFrameOptimization.cpp
llvm/lib/Target/X86/X86DynAllocaExpander.cpp
llvm/lib/Target/X86/X86FrameLowering.cpp
llvm/lib/Target/X86/X86InstrInfo.cpp
llvm/test/CodeGen/X86/materialize.ll
llvm/test/CodeGen/X86/movtopush.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.cpp
index cf1b196f10ff..bde03d400fa8 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.cpp
@@ -484,6 +484,9 @@ static bool optimizeToShortImmediateForm(MCInst &MI) {
FROM_TO(IMUL32rri, IMUL32rri8)
FROM_TO(IMUL64rmi32, IMUL64rmi8)
FROM_TO(IMUL64rri32, IMUL64rri8)
+ FROM_TO(PUSH16i, PUSH16i8)
+ FROM_TO(PUSH32i, PUSH32i8)
+ FROM_TO(PUSH64i32, PUSH64i8)
}
MCOperand &LastOp = MI.getOperand(MI.getNumOperands() - 1);
if (LastOp.isExpr()) {
diff --git a/llvm/lib/Target/X86/X86CallFrameOptimization.cpp b/llvm/lib/Target/X86/X86CallFrameOptimization.cpp
index 2bebd013a878..792bcddde707 100644
--- a/llvm/lib/Target/X86/X86CallFrameOptimization.cpp
+++ b/llvm/lib/Target/X86/X86CallFrameOptimization.cpp
@@ -521,15 +521,6 @@ void X86CallFrameOptimization::adjustCallSequence(MachineFunction &MF,
case X86::MOV32mi:
case X86::MOV64mi32:
PushOpcode = Is64Bit ? X86::PUSH64i32 : X86::PUSH32i;
- // If the operand is a small (8-bit) immediate, we can use a
- // PUSH instruction with a shorter encoding.
- // Note that isImm() may fail even though this is a MOVmi, because
- // the operand can also be a symbol.
- if (PushOp.isImm()) {
- int64_t Val = PushOp.getImm();
- if (isInt<8>(Val))
- PushOpcode = Is64Bit ? X86::PUSH64i8 : X86::PUSH32i8;
- }
Push = BuildMI(MBB, Context.Call, DL, TII->get(PushOpcode)).add(PushOp);
Push->cloneMemRefs(MF, *Store);
break;
diff --git a/llvm/lib/Target/X86/X86DynAllocaExpander.cpp b/llvm/lib/Target/X86/X86DynAllocaExpander.cpp
index 978f2db8f017..5ed94f329c4b 100644
--- a/llvm/lib/Target/X86/X86DynAllocaExpander.cpp
+++ b/llvm/lib/Target/X86/X86DynAllocaExpander.cpp
@@ -110,12 +110,10 @@ X86DynAllocaExpander::getLowering(int64_t CurrentOffset,
static bool isPushPop(const MachineInstr &MI) {
switch (MI.getOpcode()) {
- case X86::PUSH32i8:
case X86::PUSH32r:
case X86::PUSH32rmm:
case X86::PUSH32rmr:
case X86::PUSH32i:
- case X86::PUSH64i8:
case X86::PUSH64r:
case X86::PUSH64rmm:
case X86::PUSH64rmr:
diff --git a/llvm/lib/Target/X86/X86FrameLowering.cpp b/llvm/lib/Target/X86/X86FrameLowering.cpp
index 0619029aeae8..7f4f67d04f64 100644
--- a/llvm/lib/Target/X86/X86FrameLowering.cpp
+++ b/llvm/lib/Target/X86/X86FrameLowering.cpp
@@ -1756,7 +1756,7 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF,
} else {
// No initial context, store null so that there's no pointer that
// could be misused.
- BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH64i8))
+ BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH64i32))
.addImm(0)
.setMIFlag(MachineInstr::FrameSetup);
}
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index 6c1bc59d0239..d1d16dd5b3b4 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -432,13 +432,11 @@ int X86InstrInfo::getSPAdjust(const MachineInstr &MI) const {
switch (MI.getOpcode()) {
default:
return 0;
- case X86::PUSH32i8:
case X86::PUSH32r:
case X86::PUSH32rmm:
case X86::PUSH32rmr:
case X86::PUSH32i:
return 4;
- case X86::PUSH64i8:
case X86::PUSH64r:
case X86::PUSH64rmm:
case X86::PUSH64rmr:
@@ -4814,14 +4812,14 @@ static bool ExpandMOVImmSExti8(MachineInstrBuilder &MIB,
// 64-bit mode doesn't have 32-bit push/pop, so use 64-bit operations and
// widen the register if necessary.
StackAdjustment = 8;
- BuildMI(MBB, I, DL, TII.get(X86::PUSH64i8)).addImm(Imm);
+ BuildMI(MBB, I, DL, TII.get(X86::PUSH64i32)).addImm(Imm);
MIB->setDesc(TII.get(X86::POP64r));
MIB->getOperand(0)
.setReg(getX86SubSuperRegister(MIB.getReg(0), 64));
} else {
assert(MIB->getOpcode() == X86::MOV32ImmSExti8);
StackAdjustment = 4;
- BuildMI(MBB, I, DL, TII.get(X86::PUSH32i8)).addImm(Imm);
+ BuildMI(MBB, I, DL, TII.get(X86::PUSH32i)).addImm(Imm);
MIB->setDesc(TII.get(X86::POP32r));
}
MIB->removeOperand(1);
diff --git a/llvm/test/CodeGen/X86/materialize.ll b/llvm/test/CodeGen/X86/materialize.ll
index cfb9edf02b77..045e8daa7597 100644
--- a/llvm/test/CodeGen/X86/materialize.ll
+++ b/llvm/test/CodeGen/X86/materialize.ll
@@ -100,7 +100,7 @@ entry:
; CHECK32: retl
; Check push/pop have implicit def/use of $esp
-; OPERAND32: PUSH32i8 5, implicit-def $esp, implicit $esp
+; OPERAND32: PUSH32i 5, implicit-def $esp, implicit $esp
; OPERAND32-NEXT: CFI_INSTRUCTION adjust_cfa_offset 4
; OPERAND32-NEXT: renamable $ecx = POP32r implicit-def $esp, implicit $esp
; OPERAND32-NEXT: CFI_INSTRUCTION adjust_cfa_offset -4
@@ -124,7 +124,7 @@ entry:
; CHECKWIN64-NEXT: retq
; Check push/pop have implicit def/use of $rsp
-; OPERAND64: PUSH64i8 1, implicit-def $rsp, implicit $rsp
+; OPERAND64: PUSH64i32 1, implicit-def $rsp, implicit $rsp
; OPERAND64-NEXT: CFI_INSTRUCTION adjust_cfa_offset 8
; OPERAND64-NEXT: $rax = POP64r implicit-def $rsp, implicit $rsp
; OPERAND64-NEXT: CFI_INSTRUCTION adjust_cfa_offset -8
diff --git a/llvm/test/CodeGen/X86/movtopush.mir b/llvm/test/CodeGen/X86/movtopush.mir
index ddd30168a406..f92c385274be 100644
--- a/llvm/test/CodeGen/X86/movtopush.mir
+++ b/llvm/test/CodeGen/X86/movtopush.mir
@@ -34,10 +34,10 @@
---
# CHECK-LABEL: test9
# CHECK: ADJCALLSTACKDOWN32 16, 0, 16, implicit-def dead $esp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $esp, implicit $ssp
-# CHECK-NEXT: PUSH32i8 4, implicit-def $esp, implicit $esp
-# CHECK-NEXT: PUSH32i8 3, implicit-def $esp, implicit $esp
-# CHECK-NEXT: PUSH32i8 2, implicit-def $esp, implicit $esp
-# CHECK-NEXT: PUSH32i8 1, implicit-def $esp, implicit $esp
+# CHECK-NEXT: PUSH32i 4, implicit-def $esp, implicit $esp
+# CHECK-NEXT: PUSH32i 3, implicit-def $esp, implicit $esp
+# CHECK-NEXT: PUSH32i 2, implicit-def $esp, implicit $esp
+# CHECK-NEXT: PUSH32i 1, implicit-def $esp, implicit $esp
# CHECK-NEXT: CALLpcrel32 @good, csr_32, implicit $esp, implicit $ssp, implicit-def $esp, implicit-def $ssp
# CHECK-NEXT: ADJCALLSTACKUP32 16, 0, implicit-def dead $esp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $esp, implicit $ssp
# CHECK-NEXT: ADJCALLSTACKDOWN32 20, 0, 20, implicit-def dead $esp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $esp, implicit $ssp
@@ -47,7 +47,7 @@
# CHECK-NEXT: %5:gr32 = LEA32r %stack.1.q, 1, $noreg, 0, $noreg
# CHECK-NEXT: PUSH32r %4, implicit-def $esp, implicit $esp
# CHECK-NEXT: PUSH32r %5, implicit-def $esp, implicit $esp
-# CHECK-NEXT: PUSH32i8 6, implicit-def $esp, implicit $esp
+# CHECK-NEXT: PUSH32i 6, implicit-def $esp, implicit $esp
# CHECK-NEXT: PUSH32r %2, implicit-def $esp, implicit $esp
# CHECK-NEXT: PUSH32r %1, implicit-def $esp, implicit $esp
# CHECK-NEXT: CALLpcrel32 @struct, csr_32, implicit $esp, implicit $ssp, implicit-def $esp, implicit-def $ssp
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