[llvm] 0d9b36c - [X86] Remove patterns for IMUL with immediate 8 and optimize during MC lowering, NFCI
Shengchen Kan via llvm-commits
llvm-commits at lists.llvm.org
Fri May 19 20:14:21 PDT 2023
Author: Shengchen Kan
Date: 2023-05-20T11:14:03+08:00
New Revision: 0d9b36ce7d4d9e8c5bd73b73fb03b462b35539e2
URL: https://github.com/llvm/llvm-project/commit/0d9b36ce7d4d9e8c5bd73b73fb03b462b35539e2
DIFF: https://github.com/llvm/llvm-project/commit/0d9b36ce7d4d9e8c5bd73b73fb03b462b35539e2.diff
LOG: [X86] Remove patterns for IMUL with immediate 8 and optimize during MC lowering, NFCI
Added:
Modified:
llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.cpp
llvm/lib/Target/X86/X86InstrArithmetic.td
llvm/lib/Target/X86/X86InstrCompiler.td
llvm/lib/Target/X86/X86InstrInfo.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.cpp
index 8c886b6ec85c..cf1b196f10ff 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.cpp
@@ -478,6 +478,12 @@ static bool optimizeToShortImmediateForm(MCInst &MI) {
FROM_TO(CMP32ri, CMP32ri8)
FROM_TO(CMP64mi32, CMP64mi8)
FROM_TO(CMP64ri32, CMP64ri8)
+ FROM_TO(IMUL16rmi, IMUL16rmi8)
+ FROM_TO(IMUL16rri, IMUL16rri8)
+ FROM_TO(IMUL32rmi, IMUL32rmi8)
+ FROM_TO(IMUL32rri, IMUL32rri8)
+ FROM_TO(IMUL64rmi32, IMUL64rmi8)
+ FROM_TO(IMUL64rri32, IMUL64rri8)
}
MCOperand &LastOp = MI.getOperand(MI.getNumOperands() - 1);
if (LastOp.isExpr()) {
diff --git a/llvm/lib/Target/X86/X86InstrArithmetic.td b/llvm/lib/Target/X86/X86InstrArithmetic.td
index fa92e58347ab..8dfa1aa41d8a 100644
--- a/llvm/lib/Target/X86/X86InstrArithmetic.td
+++ b/llvm/lib/Target/X86/X86InstrArithmetic.td
@@ -487,11 +487,7 @@ class IMulOpRRI8<bits<8> opcode, string mnemonic, X86TypeInfo info,
X86FoldableSchedWrite sched>
: ITy<opcode, MRMSrcReg, info, (outs info.RegClass:$dst),
(ins info.RegClass:$src1, info.Imm8Operand:$src2), mnemonic,
- "{$src2, $src1, $dst|$dst, $src1, $src2}",
- [(set info.RegClass:$dst, EFLAGS,
- (X86smul_flag info.RegClass:$src1,
- info.Imm8NoSuOperator:$src2))]>,
- Sched<[sched]>{
+ "{$src2, $src1, $dst|$dst, $src1, $src2}", []>, Sched<[sched]> {
let ImmT = Imm8;
}
@@ -513,11 +509,7 @@ class IMulOpRMI8<bits<8> opcode, string mnemonic, X86TypeInfo info,
X86FoldableSchedWrite sched>
: ITy<opcode, MRMSrcMem, info, (outs info.RegClass:$dst),
(ins info.MemOperand:$src1, info.Imm8Operand:$src2), mnemonic,
- "{$src2, $src1, $dst|$dst, $src1, $src2}",
- [(set info.RegClass:$dst, EFLAGS,
- (X86smul_flag (info.LoadNode addr:$src1),
- info.Imm8NoSuOperator:$src2))]>,
- Sched<[sched.Folded]>{
+ "{$src2, $src1, $dst|$dst, $src1, $src2}", []>, Sched<[sched.Folded]> {
let ImmT = Imm8;
}
@@ -688,7 +680,6 @@ def IMUL32rm : IMulOpRM<0xAF, "imul", Xi32, WriteIMul32Reg>;
def IMUL64rm : IMulOpRM<0xAF, "imul", Xi64, WriteIMul64Reg>;
} // Constraints = "$src1 = $dst"
} // Defs = [EFLAGS]
-} // hasSideEffects
// Surprisingly enough, these are not two address instructions!
let Defs = [EFLAGS] in {
@@ -700,10 +691,10 @@ let Defs = [EFLAGS] in {
def IMUL16rri8 : IMulOpRRI8<0x6B, "imul", Xi16, WriteIMul16Imm>;
// GR16 = GR16*I16
def IMUL16rri : IMulOpRRI<0x69, "imul", Xi16, WriteIMul16Imm>;
-// GR32 = GR32*I32
-def IMUL32rri : IMulOpRRI<0x69, "imul", Xi32, WriteIMul32Imm>;
// GR32 = GR32*I8
def IMUL32rri8 : IMulOpRRI8<0x6B, "imul", Xi32, WriteIMul32Imm>;
+// GR32 = GR32*I32
+def IMUL32rri : IMulOpRRI<0x69, "imul", Xi32, WriteIMul32Imm>;
// GR64 = GR64*I8
def IMUL64rri8 : IMulOpRRI8<0x6B, "imul", Xi64, WriteIMul64Imm>;
// GR64 = GR64*I32
@@ -711,6 +702,7 @@ def IMUL64rri32 : IMulOpRRI<0x69, "imul", Xi64, WriteIMul64Imm>;
// Memory-Integer Signed Integer Multiply
// GR16 = [mem16]*I8
+let mayLoad = 1 in {
def IMUL16rmi8 : IMulOpRMI8<0x6B, "imul", Xi16, WriteIMul16Imm>;
// GR16 = [mem16]*I16
def IMUL16rmi : IMulOpRMI<0x69, "imul", Xi16, WriteIMul16Imm>;
@@ -722,7 +714,9 @@ def IMUL32rmi : IMulOpRMI<0x69, "imul", Xi32, WriteIMul32Imm>;
def IMUL64rmi8 : IMulOpRMI8<0x6B, "imul", Xi64, WriteIMul64Imm>;
// GR64 = [mem64]*I32
def IMUL64rmi32 : IMulOpRMI<0x69, "imul", Xi64, WriteIMul64Imm>;
+} // mayLoad
} // Defs = [EFLAGS]
+} // hasSideEffects
// unsigned division/remainder
let hasSideEffects = 1 in { // so that we don't speculatively execute
diff --git a/llvm/lib/Target/X86/X86InstrCompiler.td b/llvm/lib/Target/X86/X86InstrCompiler.td
index cd0cdf6cb002..52750937c425 100644
--- a/llvm/lib/Target/X86/X86InstrCompiler.td
+++ b/llvm/lib/Target/X86/X86InstrCompiler.td
@@ -2084,12 +2084,6 @@ def : Pat<(mul GR16:$src1, imm:$src2),
(IMUL16rri GR16:$src1, imm:$src2)>;
def : Pat<(mul GR32:$src1, imm:$src2),
(IMUL32rri GR32:$src1, imm:$src2)>;
-def : Pat<(mul GR16:$src1, i16immSExt8:$src2),
- (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
-def : Pat<(mul GR32:$src1, i32immSExt8:$src2),
- (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
-def : Pat<(mul GR64:$src1, i64immSExt8:$src2),
- (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
def : Pat<(mul GR64:$src1, i64immSExt32:$src2),
(IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
@@ -2098,12 +2092,6 @@ def : Pat<(mul (loadi16 addr:$src1), imm:$src2),
(IMUL16rmi addr:$src1, imm:$src2)>;
def : Pat<(mul (loadi32 addr:$src1), imm:$src2),
(IMUL32rmi addr:$src1, imm:$src2)>;
-def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2),
- (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
-def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2),
- (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
-def : Pat<(mul (loadi64 addr:$src1), i64immSExt8:$src2),
- (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2),
(IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index 2dff9ceeffde..708943fd9da1 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -218,14 +218,11 @@ bool X86InstrInfo::isDataInvariantLoad(MachineInstr &MI) {
// However, they set flags and are perhaps the most surprisingly constant
// time operations so we call them out here separately.
case X86::IMUL16rm:
- case X86::IMUL16rmi8:
case X86::IMUL16rmi:
case X86::IMUL32rm:
- case X86::IMUL32rmi8:
case X86::IMUL32rmi:
case X86::IMUL64rm:
case X86::IMUL64rmi32:
- case X86::IMUL64rmi8:
// Bit scanning and counting instructions that are somewhat surprisingly
// constant time as they scan across bits and do other fairly complex
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