[llvm] 1e6d069 - [RISCV] Simplify and improve getLMULCost.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-05-19T14:09:50-07:00
New Revision: 1e6d069709f32adcd6e1e8bedff621351cc43d34

URL: https://github.com/llvm/llvm-project/commit/1e6d069709f32adcd6e1e8bedff621351cc43d34
DIFF: https://github.com/llvm/llvm-project/commit/1e6d069709f32adcd6e1e8bedff621351cc43d34.diff

LOG: [RISCV] Simplify and improve getLMULCost.

Use divideCeil for fixed vectors which avoids the need for a std::max
with 1 and should be more correct for odd sized vectors if those
occur.

Use conditional operator instead of an if/else.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index 4a0f8c76a415..34626e249e7b 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -45,14 +45,11 @@ InstructionCost RISCVTTIImpl::getLMULCost(MVT VT) {
     bool Fractional;
     std::tie(LMul, Fractional) =
         RISCVVType::decodeVLMUL(RISCVTargetLowering::getLMUL(VT));
-    if (Fractional)
-      Cost = 1;
-    else
-      Cost = LMul;
+    Cost = Fractional ? 1 : LMul;
   } else {
-    Cost = VT.getSizeInBits() / ST->getRealMinVLen();
+    Cost = divideCeil(VT.getSizeInBits(), ST->getRealMinVLen());
   }
-  return std::max<unsigned>(Cost, 1);
+  return Cost;
 }
 
 InstructionCost RISCVTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty,