[PATCH] D149711: [PowerPC] Remove asserts from the disassembler.
Stefan Pintilie via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri May 19 12:07:20 PDT 2023
stefanp updated this revision to Diff 523887.
stefanp added a comment.
Added the conditions so that we return DecodeStatus::Fail instead of asserting.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D149711/new/
https://reviews.llvm.org/D149711
Files:
llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp-invalid.txt
Index: llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp-invalid.txt
===================================================================
--- /dev/null
+++ llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp-invalid.txt
@@ -0,0 +1,7 @@
+# RUN: llvm-mc --disassemble %s -mcpu=pwr10 -triple \
+# RUN: powerpc64-unknown-linux-gnu < %s 2>&1 | FileCheck %s
+
+# Regsiter for DSUBQ cannot be greater than 30.
+# CHECK-NOT: dsubq 0, 6, 31
+# CHECK: warning: invalid instruction encoding
+0xfc 0x06 0xfc 0x04
Index: llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
===================================================================
--- llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
+++ llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
@@ -83,7 +83,8 @@
template <std::size_t N>
static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo,
const MCPhysReg (&Regs)[N]) {
- assert(RegNo < N && "Invalid register number");
+ if (RegNo >= N)
+ return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createReg(Regs[RegNo]));
return MCDisassembler::Success;
}
@@ -115,8 +116,8 @@
static DecodeStatus DecodeFpRCRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
const MCDisassembler *Decoder) {
- assert(RegNo <= 30 && "Expecting a register number no more than 30.");
- assert((RegNo & 1) == 0 && "Expecting an even register number.");
+ if (RegNo > 30 || (RegNo & 1))
+ return MCDisassembler::Fail;
return decodeRegisterClass(Inst, RegNo >> 1, FpRegs);
}
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