[llvm] aa144fb - [AMDGPU] Fix warnings
Kazu Hirata via llvm-commits
llvm-commits at lists.llvm.org
Fri May 19 10:56:33 PDT 2023
Author: Kazu Hirata
Date: 2023-05-19T10:56:23-07:00
New Revision: aa144fbeaf213d93f8a244a353db4c3301d8b1b0
URL: https://github.com/llvm/llvm-project/commit/aa144fbeaf213d93f8a244a353db4c3301d8b1b0
DIFF: https://github.com/llvm/llvm-project/commit/aa144fbeaf213d93f8a244a353db4c3301d8b1b0.diff
LOG: [AMDGPU] Fix warnings
This patch fixes warnings like:
llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h:711: warning:
enumerated and non-enumerated type in conditional expression
Added:
Modified:
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index 67057fd0e5dc..48be4ce35c0f 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -4979,7 +4979,7 @@ void AMDGPUInstructionSelector::renderOpSelTImm(MachineInstrBuilder &MIB,
const MachineInstr &MI,
int OpIdx) const {
assert(OpIdx >= 0 && "expected to match an immediate operand");
- MIB.addImm(MI.getOperand(OpIdx).getImm() ? SISrcMods::OP_SEL_0 : 0);
+ MIB.addImm(MI.getOperand(OpIdx).getImm() ? (int64_t)SISrcMods::OP_SEL_0 : 0);
}
void AMDGPUInstructionSelector::renderExtractCPol(MachineInstrBuilder &MIB,
diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
index 59f84cd63a50..df3abdfb6531 100644
--- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
@@ -699,7 +699,8 @@ class SIMachineFunctionInfo final : public AMDGPUMachineFunction {
// Add system SGPRs.
Register addWorkGroupIDX(bool HasArchitectedSGPRs) {
- Register Reg = HasArchitectedSGPRs ? AMDGPU::TTMP9 : getNextSystemSGPR();
+ Register Reg =
+ HasArchitectedSGPRs ? (MCPhysReg)AMDGPU::TTMP9 : getNextSystemSGPR();
ArgInfo.WorkGroupIDX = ArgDescriptor::createRegister(Reg);
if (!HasArchitectedSGPRs)
NumSystemSGPRs += 1;
@@ -708,7 +709,8 @@ class SIMachineFunctionInfo final : public AMDGPUMachineFunction {
}
Register addWorkGroupIDY(bool HasArchitectedSGPRs) {
- Register Reg = HasArchitectedSGPRs ? AMDGPU::TTMP7 : getNextSystemSGPR();
+ Register Reg =
+ HasArchitectedSGPRs ? (MCPhysReg)AMDGPU::TTMP7 : getNextSystemSGPR();
unsigned Mask = HasArchitectedSGPRs && hasWorkGroupIDZ() ? 0xffff : ~0u;
ArgInfo.WorkGroupIDY = ArgDescriptor::createRegister(Reg, Mask);
if (!HasArchitectedSGPRs)
@@ -718,7 +720,8 @@ class SIMachineFunctionInfo final : public AMDGPUMachineFunction {
}
Register addWorkGroupIDZ(bool HasArchitectedSGPRs) {
- Register Reg = HasArchitectedSGPRs ? AMDGPU::TTMP7 : getNextSystemSGPR();
+ Register Reg =
+ HasArchitectedSGPRs ? (MCPhysReg)AMDGPU::TTMP7 : getNextSystemSGPR();
unsigned Mask = HasArchitectedSGPRs ? 0xffff << 16 : ~0u;
ArgInfo.WorkGroupIDZ = ArgDescriptor::createRegister(Reg, Mask);
if (!HasArchitectedSGPRs)
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