[PATCH] D150951: [AArch64][SME2/SVE2p1] Add predicate-as-counter intrinsics for sel

[Caroline via Phabricator via llvm-commits]

CarolineConcatto accepted this revision.
CarolineConcatto added inline comments.
This revision is now accepted and ready to land.


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Comment at: llvm/test/CodeGen/AArch64/sve2p1-intrinsics-selx4.ll:22
+; CHECK-NEXT:    mov z28.d, z1.d
+; CHECK-NEXT:    sel { z0.b - z3.b }, pn8, { z28.b - z31.b }, { z24.b - z27.b }
+; CHECK-NEXT:    ldr p8, [sp, #7, mul vl] // 2-byte Folded Reload
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Nothing related to the patch, but I was wondering why the last sve registers and not z4 to z16?


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https://reviews.llvm.org/D150951