[PATCH] D150671: RISCV/InstrInfo: model register pressure for MICombiner

[Ramkumar Ramachandra via Phabricator via llvm-commits]

artagnon added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:1573-1595
 bool RISCVInstrInfo::getMachineCombinerPatterns(
     MachineInstr &Root, SmallVectorImpl<MachineCombinerPattern> &Patterns,
     bool DoRegPressureReduce) const {
+  unsigned Opc = Root.getOpcode();
+  bool IsFAdd = isFADD(Opc);
 
+  if (IsFAdd || isFSUB(Opc)) {
----------------
kito-cheng wrote:
> It seems like just a NFC refactor? if so this should split into a separated patch.
It's not an NFC refactor. Notice `if (DoRegPressureReduce) return false;`


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D150671/new/

https://reviews.llvm.org/D150671