[PATCH] D150959: [SVE2p1] Add a reinterpret intrinsic for svcount_t to/from svbool_t.

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen created this revision.
sdesmalen added reviewers: CarolineConcatto, david-arm.
Herald added subscribers: hiraditya, tschuett.
Herald added a project: All.
sdesmalen requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

These intrinsics can be used to implement existing operations on svcount_t
when the actual bits/content of the predicate register doesn't matter (such
as PSEL, which copies the full contents of the first source register to the
destination register).


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D150959

Files:
  llvm/include/llvm/IR/IntrinsicsAArch64.td
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/sme2-intrinsics-reinterpret-svbool-svcount.ll


Index: llvm/test/CodeGen/AArch64/sme2-intrinsics-reinterpret-svbool-svcount.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/sme2-intrinsics-reinterpret-svbool-svcount.ll
@@ -0,0 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2 < %s | FileCheck %s
+
+define <vscale x 16 x i1> @reinterpret_to_nxv16i1(target("aarch64.svcount") %pg) {
+; CHECK-LABEL: reinterpret_to_nxv16i1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ret
+  %out = call <vscale x 16 x i1> @llvm.aarch64.sve.reinterpret.from.svcount(target("aarch64.svcount") %pg)
+  ret <vscale x 16 x i1> %out
+}
+
+define target("aarch64.svcount") @reinterpret_from_nxv16i1(<vscale x 16 x i1>  %pg) {
+; CHECK-LABEL: reinterpret_from_nxv16i1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ret
+  %out = call target("aarch64.svcount") @llvm.aarch64.sve.reinterpret.to.svcount(<vscale x 16 x i1> %pg)
+  ret target("aarch64.svcount") %out
+}
+
+declare <vscale x 16 x i1>@llvm.aarch64.sve.reinterpret.from.svcount(target("aarch64.svcount"))
+declare target("aarch64.svcount")@llvm.aarch64.sve.reinterpret.to.svcount(<vscale x 16 x i1>)
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -5038,6 +5038,9 @@
   }
   case Intrinsic::aarch64_sve_dupq_lane:
     return LowerDUPQLane(Op, DAG);
+  case Intrinsic::aarch64_sve_reinterpret_to_svcount:
+  case Intrinsic::aarch64_sve_reinterpret_from_svcount:
+    return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Op.getOperand(1));
   case Intrinsic::aarch64_sve_convert_from_svbool:
     return getSVEPredicateBitCast(Op.getValueType(), Op.getOperand(1), DAG);
   case Intrinsic::aarch64_sve_convert_to_svbool:
Index: llvm/include/llvm/IR/IntrinsicsAArch64.td
===================================================================
--- llvm/include/llvm/IR/IntrinsicsAArch64.td
+++ llvm/include/llvm/IR/IntrinsicsAArch64.td
@@ -2113,6 +2113,13 @@
                                                   [llvm_anyvector_ty],
                                                   [IntrNoMem]>;
 
+def int_aarch64_sve_reinterpret_to_svcount : DefaultAttrsIntrinsic<[llvm_aarch64_svcount_ty],
+                                                    [llvm_nxv16i1_ty],
+                                                    [IntrNoMem]>;
+
+def int_aarch64_sve_reinterpret_from_svcount : DefaultAttrsIntrinsic<[llvm_nxv16i1_ty],
+                                                  [llvm_aarch64_svcount_ty],
+                                                  [IntrNoMem]>;
 //
 // Gather loads: scalar base + vector offsets
 //


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D150959.523724.patch
Type: text/x-patch
Size: 2839 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20230519/75e29234/attachment.bin>