[PATCH] D150950: MachineCombiner/RISCV: add test for register pressure

[Ramkumar Ramachandra via Phabricator via llvm-commits]

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In preparation for a patch, add a test for MachineCombiner in RISC-V
CodeGen, where the MachineBasicBlock has 33 live registers (just above
the general-purpose register limit of 32 on RISC-V). Since
MachineCombiner kicks in, it leads to increased register pressure,
resulting in spills. The next patch will turn off MachineCombiner for
this case.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D150950

Files:
  llvm/test/CodeGen/RISCV/machine-combiner.ll

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