[PATCH] D150935: [NFC][RISCV] Replace global def containing only one field with defvar
Wang Pengcheng via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu May 18 23:47:40 PDT 2023
pcwang-thead created this revision.
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This simplifies some code.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D150935
Files:
llvm/lib/Target/RISCV/RISCVRegisterInfo.td
Index: llvm/lib/Target/RISCV/RISCVRegisterInfo.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -342,9 +342,7 @@
defvar vbool64_t = nxv1i1;
// There is no need to define register classes for fractional LMUL.
-def LMULList {
- list<int> m = [1, 2, 4, 8];
-}
+defvar LMULList = [1, 2, 4, 8];
//===----------------------------------------------------------------------===//
// Utility classes for segment load/store.
@@ -576,7 +574,7 @@
(add (sequence "V%u", 8, 31),
(sequence "V%u", 0, 7)), 1>;
-foreach m = LMULList.m in {
+foreach m = LMULList in {
foreach nf = NFList<m>.L in {
def "VRN" # nf # "M" # m # "NoV0": VReg<[untyped],
(add !cast<RegisterTuples>("VN" # nf # "M" # m # "NoV0")),
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