[llvm] 9615d48 - [AMDGPU][Uniformity] SI_IF and SI_ELSE pseudos are always divergent
Sameer Sahasrabuddhe via llvm-commits
llvm-commits at lists.llvm.org
Thu May 18 23:20:02 PDT 2023
Author: Sameer Sahasrabuddhe
Date: 2023-05-19T11:49:09+05:30
New Revision: 9615d48540a2d3615df91ae7f053bb5effb72e8e
URL: https://github.com/llvm/llvm-project/commit/9615d48540a2d3615df91ae7f053bb5effb72e8e
DIFF: https://github.com/llvm/llvm-project/commit/9615d48540a2d3615df91ae7f053bb5effb72e8e.diff
LOG: [AMDGPU][Uniformity] SI_IF and SI_ELSE pseudos are always divergent
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D150861
Added:
llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/control-flow-intrinsics.mir
Modified:
llvm/include/llvm/ADT/GenericUniformityImpl.h
llvm/lib/Target/AMDGPU/SIInstructions.td
Removed:
################################################################################
diff --git a/llvm/include/llvm/ADT/GenericUniformityImpl.h b/llvm/include/llvm/ADT/GenericUniformityImpl.h
index 71935d12ea03f..b6d4424fbb453 100644
--- a/llvm/include/llvm/ADT/GenericUniformityImpl.h
+++ b/llvm/include/llvm/ADT/GenericUniformityImpl.h
@@ -1147,9 +1147,11 @@ template <typename ContextT>
void GenericUniformityAnalysisImpl<ContextT>::print(raw_ostream &OS) const {
bool haveDivergentArgs = false;
- if (DivergentValues.empty()) {
- assert(DivergentTermBlocks.empty());
- assert(DivergentExitCycles.empty());
+ // Control flow instructions may be divergent even if their inputs are
+ // uniform. Thus, although exceedingly rare, it is possible to have a program
+ // with no divergent values but with divergent control structures.
+ if (DivergentValues.empty() && DivergentTermBlocks.empty() &&
+ DivergentExitCycles.empty()) {
OS << "ALL VALUES UNIFORM\n";
return;
}
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index 0c67de58d602a..31914cc07eeaa 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -397,6 +397,7 @@ def SI_IF: CFPseudoInstSI <
let Constraints = "";
let Size = 12;
let hasSideEffects = 1;
+ let IsNeverUniform = 1;
}
def SI_ELSE : CFPseudoInstSI <
@@ -404,6 +405,7 @@ def SI_ELSE : CFPseudoInstSI <
(ins SReg_1:$src, brtarget:$target), [], 1, 1> {
let Size = 12;
let hasSideEffects = 1;
+ let IsNeverUniform = 1;
}
def SI_WATERFALL_LOOP : CFPseudoInstSI <
diff --git a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/control-flow-intrinsics.mir b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/control-flow-intrinsics.mir
new file mode 100644
index 0000000000000..dec55e5662c8c
--- /dev/null
+++ b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/control-flow-intrinsics.mir
@@ -0,0 +1,39 @@
+# RUN: llc -mtriple=amdgcn-- -mcpu=gfx900 -run-pass=print-machine-uniformity -o - %s 2>&1 | FileCheck %s
+
+---
+name: f1
+body: |
+ ; CHECK-LABEL: MachineUniformityInfo for function: f1
+ bb.0:
+ successors: %bb.1, %bb.2
+
+ ; CHECK-NOT: DIVERGENT: %1
+ %1:sreg_64(s64) = G_IMPLICIT_DEF
+ ; CHECK: DIVERGENT: {{.*}} SI_IF
+ %2:sreg_64 = SI_IF %1, %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
+
+ bb.1:
+ SI_RETURN
+
+ bb.2:
+ G_BR %bb.1
+
+...
+
+---
+name: f2
+body: |
+ ; CHECK-LABEL: MachineUniformityInfo for function: f2
+ bb.0:
+ successors: %bb.1, %bb.2
+
+ ; CHECK-NOT: DIVERGENT: %1
+ %1:sreg_64(s64) = G_IMPLICIT_DEF
+ ; CHECK: DIVERGENT: {{.*}} SI_ELSE
+ %2:sreg_64 = SI_ELSE %1, %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
+
+ bb.1:
+ SI_RETURN
+
+ bb.2:
+ G_BR %bb.1
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