[PATCH] D150787: [PowerPC] Add DFP multiply and divide instructions.

[Stefan Pintilie via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGdf367da5a683: [PowerPC] Add DFP multiply and divide instructions. (authored by stefanp).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D150787/new/

https://reviews.llvm.org/D150787

Files:
  llvm/lib/Target/PowerPC/PPCInstrDFP.td
  llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp.txt
  llvm/test/MC/PowerPC/ppc64-encoding-dfp.s


Index: llvm/test/MC/PowerPC/ppc64-encoding-dfp.s
===================================================================
--- llvm/test/MC/PowerPC/ppc64-encoding-dfp.s
+++ llvm/test/MC/PowerPC/ppc64-encoding-dfp.s
@@ -26,3 +26,27 @@
 # CHECK-BE: dsubq. 2, 6, 4                 # encoding: [0xfc,0x46,0x24,0x05]
 # CHECK-LE: dsubq. 2, 6, 4                 # encoding: [0x05,0x24,0x46,0xfc]
             dsubq. 2, 6, 4
+# CHECK-BE: dmul 2, 3, 4                   # encoding: [0xec,0x43,0x20,0x44]
+# CHECK-LE: dmul 2, 3, 4                   # encoding: [0x44,0x20,0x43,0xec]
+            dmul 2, 3, 4
+# CHECK-BE: dmul. 2, 3, 4                  # encoding: [0xec,0x43,0x20,0x45]
+# CHECK-LE: dmul. 2, 3, 4                  # encoding: [0x45,0x20,0x43,0xec]
+            dmul. 2, 3, 4
+# CHECK-BE: dmulq 2, 6, 4                  # encoding: [0xfc,0x46,0x20,0x44]
+# CHECK-LE: dmulq 2, 6, 4                  # encoding: [0x44,0x20,0x46,0xfc]
+            dmulq 2, 6, 4
+# CHECK-BE: dmulq. 2, 6, 4                 # encoding: [0xfc,0x46,0x20,0x45]
+# CHECK-LE: dmulq. 2, 6, 4                 # encoding: [0x45,0x20,0x46,0xfc]
+            dmulq. 2, 6, 4
+# CHECK-BE: ddiv 2, 3, 4                   # encoding: [0xec,0x43,0x24,0x44]
+# CHECK-LE: ddiv 2, 3, 4                   # encoding: [0x44,0x24,0x43,0xec]
+            ddiv 2, 3, 4
+# CHECK-BE: ddiv. 2, 3, 4                  # encoding: [0xec,0x43,0x24,0x45]
+# CHECK-LE: ddiv. 2, 3, 4                  # encoding: [0x45,0x24,0x43,0xec]
+            ddiv. 2, 3, 4
+# CHECK-BE: ddivq 2, 6, 4                  # encoding: [0xfc,0x46,0x24,0x44]
+# CHECK-LE: ddivq 2, 6, 4                  # encoding: [0x44,0x24,0x46,0xfc]
+            ddivq 2, 6, 4
+# CHECK-BE: ddivq. 2, 6, 4                 # encoding: [0xfc,0x46,0x24,0x45]
+# CHECK-LE: ddivq. 2, 6, 4                 # encoding: [0x45,0x24,0x46,0xfc]
+            ddivq. 2, 6, 4
Index: llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp.txt
===================================================================
--- llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp.txt
+++ llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp.txt
@@ -23,3 +23,27 @@
 
 # CHECK: dsubq. 2, 6, 4
 0xfc 0x46 0x24 0x05
+
+# CHECK: dmul 2, 3, 4
+0xec 0x43 0x20 0x44
+
+# CHECK: dmul. 2, 3, 4
+0xec 0x43 0x20 0x45
+
+# CHECK: dmulq 2, 6, 4
+0xfc 0x46 0x20 0x44
+
+# CHECK: dmulq. 2, 6, 4
+0xfc 0x46 0x20 0x45
+
+# CHECK: ddiv 2, 3, 4
+0xec 0x43 0x24 0x44
+
+# CHECK: ddiv. 2, 3, 4
+0xec 0x43 0x24 0x45
+
+# CHECK: ddivq 2, 6, 4
+0xfc 0x46 0x24 0x44
+
+# CHECK: ddivq. 2, 6, 4
+0xfc 0x46 0x24 0x45
Index: llvm/lib/Target/PowerPC/PPCInstrDFP.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrDFP.td
+++ llvm/lib/Target/PowerPC/PPCInstrDFP.td
@@ -24,5 +24,17 @@
 
 defm DSUBQ : XForm_28r<63, 514, (outs fpairrc:$RST), (ins fpairrc:$RA, fpairrc:$RB),
                        "dsubq",  "$RST, $RA, $RB", IIC_FPGeneral, []>;
+
+defm DMUL : XForm_28r<59, 34, (outs f8rc:$RST), (ins f8rc:$RA, f8rc:$RB),
+                      "dmul",  "$RST, $RA, $RB", IIC_FPGeneral, []>;
+
+defm DMULQ : XForm_28r<63, 34, (outs fpairrc:$RST), (ins fpairrc:$RA, fpairrc:$RB),
+                       "dmulq",  "$RST, $RA, $RB", IIC_FPGeneral, []>;
+
+defm DDIV : XForm_28r<59, 546, (outs f8rc:$RST), (ins f8rc:$RA, f8rc:$RB),
+                      "ddiv",  "$RST, $RA, $RB", IIC_FPGeneral, []>;
+
+defm DDIVQ : XForm_28r<63, 546, (outs fpairrc:$RST), (ins fpairrc:$RA, fpairrc:$RB),
+                       "ddivq",  "$RST, $RA, $RB", IIC_FPGeneral, []>;
 }
 


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