[llvm] df367da - [PowerPC] Add DFP multiply and divide instructions.

[Stefan Pintilie via llvm-commits]

Author: Stefan Pintilie
Date: 2023-05-18T10:36:12-04:00
New Revision: df367da5a68363df2f2dd55c26a9655c13da4715

URL: https://github.com/llvm/llvm-project/commit/df367da5a68363df2f2dd55c26a9655c13da4715
DIFF: https://github.com/llvm/llvm-project/commit/df367da5a68363df2f2dd55c26a9655c13da4715.diff

LOG: [PowerPC] Add DFP multiply and divide instructions.

This patch adds the DFP mul and div instructions. This includes both the
double and quad forms of the instructions as well as the record form.

Reviewed By: amyk

Differential Revision: https://reviews.llvm.org/D150787

Added: 
    

Modified: 
    llvm/lib/Target/PowerPC/PPCInstrDFP.td
    llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp.txt
    llvm/test/MC/PowerPC/ppc64-encoding-dfp.s

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/PowerPC/PPCInstrDFP.td b/llvm/lib/Target/PowerPC/PPCInstrDFP.td
index be13ed9b69c5b..56847b4fadf46 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrDFP.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrDFP.td
@@ -24,5 +24,17 @@ defm DSUB : XForm_28r<59, 514, (outs f8rc:$RST), (ins f8rc:$RA, f8rc:$RB),
 
 defm DSUBQ : XForm_28r<63, 514, (outs fpairrc:$RST), (ins fpairrc:$RA, fpairrc:$RB),
                        "dsubq",  "$RST, $RA, $RB", IIC_FPGeneral, []>;
+
+defm DMUL : XForm_28r<59, 34, (outs f8rc:$RST), (ins f8rc:$RA, f8rc:$RB),
+                      "dmul",  "$RST, $RA, $RB", IIC_FPGeneral, []>;
+
+defm DMULQ : XForm_28r<63, 34, (outs fpairrc:$RST), (ins fpairrc:$RA, fpairrc:$RB),
+                       "dmulq",  "$RST, $RA, $RB", IIC_FPGeneral, []>;
+
+defm DDIV : XForm_28r<59, 546, (outs f8rc:$RST), (ins f8rc:$RA, f8rc:$RB),
+                      "ddiv",  "$RST, $RA, $RB", IIC_FPGeneral, []>;
+
+defm DDIVQ : XForm_28r<63, 546, (outs fpairrc:$RST), (ins fpairrc:$RA, fpairrc:$RB),
+                       "ddivq",  "$RST, $RA, $RB", IIC_FPGeneral, []>;
 }
 

diff  --git a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp.txt
index 3b7fa5f4e3bd5..126aad4cc3f4e 100644
--- a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp.txt
@@ -23,3 +23,27 @@
 
 # CHECK: dsubq. 2, 6, 4
 0xfc 0x46 0x24 0x05
+
+# CHECK: dmul 2, 3, 4
+0xec 0x43 0x20 0x44
+
+# CHECK: dmul. 2, 3, 4
+0xec 0x43 0x20 0x45
+
+# CHECK: dmulq 2, 6, 4
+0xfc 0x46 0x20 0x44
+
+# CHECK: dmulq. 2, 6, 4
+0xfc 0x46 0x20 0x45
+
+# CHECK: ddiv 2, 3, 4
+0xec 0x43 0x24 0x44
+
+# CHECK: ddiv. 2, 3, 4
+0xec 0x43 0x24 0x45
+
+# CHECK: ddivq 2, 6, 4
+0xfc 0x46 0x24 0x44
+
+# CHECK: ddivq. 2, 6, 4
+0xfc 0x46 0x24 0x45

diff  --git a/llvm/test/MC/PowerPC/ppc64-encoding-dfp.s b/llvm/test/MC/PowerPC/ppc64-encoding-dfp.s
index 4b76bd21c7911..256ca98402d4e 100644
--- a/llvm/test/MC/PowerPC/ppc64-encoding-dfp.s
+++ b/llvm/test/MC/PowerPC/ppc64-encoding-dfp.s
@@ -26,3 +26,27 @@
 # CHECK-BE: dsubq. 2, 6, 4                 # encoding: [0xfc,0x46,0x24,0x05]
 # CHECK-LE: dsubq. 2, 6, 4                 # encoding: [0x05,0x24,0x46,0xfc]
             dsubq. 2, 6, 4
+# CHECK-BE: dmul 2, 3, 4                   # encoding: [0xec,0x43,0x20,0x44]
+# CHECK-LE: dmul 2, 3, 4                   # encoding: [0x44,0x20,0x43,0xec]
+            dmul 2, 3, 4
+# CHECK-BE: dmul. 2, 3, 4                  # encoding: [0xec,0x43,0x20,0x45]
+# CHECK-LE: dmul. 2, 3, 4                  # encoding: [0x45,0x20,0x43,0xec]
+            dmul. 2, 3, 4
+# CHECK-BE: dmulq 2, 6, 4                  # encoding: [0xfc,0x46,0x20,0x44]
+# CHECK-LE: dmulq 2, 6, 4                  # encoding: [0x44,0x20,0x46,0xfc]
+            dmulq 2, 6, 4
+# CHECK-BE: dmulq. 2, 6, 4                 # encoding: [0xfc,0x46,0x20,0x45]
+# CHECK-LE: dmulq. 2, 6, 4                 # encoding: [0x45,0x20,0x46,0xfc]
+            dmulq. 2, 6, 4
+# CHECK-BE: ddiv 2, 3, 4                   # encoding: [0xec,0x43,0x24,0x44]
+# CHECK-LE: ddiv 2, 3, 4                   # encoding: [0x44,0x24,0x43,0xec]
+            ddiv 2, 3, 4
+# CHECK-BE: ddiv. 2, 3, 4                  # encoding: [0xec,0x43,0x24,0x45]
+# CHECK-LE: ddiv. 2, 3, 4                  # encoding: [0x45,0x24,0x43,0xec]
+            ddiv. 2, 3, 4
+# CHECK-BE: ddivq 2, 6, 4                  # encoding: [0xfc,0x46,0x24,0x44]
+# CHECK-LE: ddivq 2, 6, 4                  # encoding: [0x44,0x24,0x46,0xfc]
+            ddivq 2, 6, 4
+# CHECK-BE: ddivq. 2, 6, 4                 # encoding: [0xfc,0x46,0x24,0x45]
+# CHECK-LE: ddivq. 2, 6, 4                 # encoding: [0x45,0x24,0x46,0xfc]
+            ddivq. 2, 6, 4