[PATCH] D150855: MachineCombiner: consider all uses in getLatency()

[Ramkumar Ramachandra via Phabricator via llvm-commits]

artagnon updated this revision to Diff 523345.
artagnon added a comment.

Address review comments. There are no test changes, but Embench shows a minor improvement in one test.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D150855/new/

https://reviews.llvm.org/D150855

Files:
  llvm/lib/CodeGen/MachineCombiner.cpp


Index: llvm/lib/CodeGen/MachineCombiner.cpp
===================================================================
--- llvm/lib/CodeGen/MachineCombiner.cpp
+++ llvm/lib/CodeGen/MachineCombiner.cpp
@@ -278,21 +278,17 @@
       continue;
     if (!MO.isDef())
       continue;
-    // Get the first instruction that uses MO
-    MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(MO.getReg());
-    RI++;
-    if (RI == MRI->reg_end())
-      continue;
-    MachineInstr *UseMO = RI->getParent();
-    unsigned LatencyOp = 0;
-    if (UseMO && BlockTrace.isDepInTrace(*Root, *UseMO)) {
-      LatencyOp = TSchedModel.computeOperandLatency(
-          NewRoot, NewRoot->findRegisterDefOperandIdx(MO.getReg()), UseMO,
-          UseMO->findRegisterUseOperandIdx(MO.getReg()));
-    } else {
-      LatencyOp = TSchedModel.computeInstrLatency(NewRoot);
+    for (MachineInstr &UseInstr : MRI->use_nodbg_instructions(MO.getReg())) {
+      unsigned LatencyOp = 0;
+      if (BlockTrace.isDepInTrace(*Root, UseInstr)) {
+        LatencyOp = TSchedModel.computeOperandLatency(
+            NewRoot, NewRoot->findRegisterDefOperandIdx(MO.getReg()), &UseInstr,
+            MO.getOperandNo());
+      } else {
+        LatencyOp = TSchedModel.computeInstrLatency(NewRoot);
+      }
+      NewRootLatency = std::max(NewRootLatency, LatencyOp);
     }
-    NewRootLatency = std::max(NewRootLatency, LatencyOp);
   }
   return NewRootLatency;
 }


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