[PATCH] D150599: [ARC] Use backwards scavenging in frame index elimination

[Jay Foad via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGa8dd9f42b7f4: [ARC] Use backwards scavenging in frame index elimination (authored by foad).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D150599/new/

https://reviews.llvm.org/D150599

Files:
  llvm/lib/Target/ARC/ARCRegisterInfo.cpp
  llvm/lib/Target/ARC/ARCRegisterInfo.h


Index: llvm/lib/Target/ARC/ARCRegisterInfo.h
===================================================================
--- llvm/lib/Target/ARC/ARCRegisterInfo.h
+++ llvm/lib/Target/ARC/ARCRegisterInfo.h
@@ -39,6 +39,8 @@
 
   bool useFPForScavengingIndex(const MachineFunction &MF) const override;
 
+  bool supportsBackwardScavenger() const override { return true; }
+
   bool eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
                            unsigned FIOperandNum,
                            RegScavenger *RS = nullptr) const override;
Index: llvm/lib/Target/ARC/ARCRegisterInfo.cpp
===================================================================
--- llvm/lib/Target/ARC/ARCRegisterInfo.cpp
+++ llvm/lib/Target/ARC/ARCRegisterInfo.cpp
@@ -63,7 +63,8 @@
       // of the load offset.
       const TargetRegisterInfo *TRI =
           MBB.getParent()->getSubtarget().getRegisterInfo();
-      BaseReg = RS->scavengeRegister(&ARC::GPR32RegClass, II, SPAdj);
+      BaseReg =
+          RS->scavengeRegisterBackwards(ARC::GPR32RegClass, II, false, SPAdj);
       assert(BaseReg && "Register scavenging failed.");
       LLVM_DEBUG(dbgs() << "Scavenged register " << printReg(BaseReg, TRI)
                         << " for FrameReg=" << printReg(FrameReg, TRI)


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