[PATCH] D150759: [AMDGPU][Uniformity] V_MBCNT* is never uniform
Carl Ritson via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed May 17 21:50:57 PDT 2023
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG9602c7a0817f: [AMDGPU][Uniformity] V_MBCNT* is never uniform (authored by critson).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D150759/new/
https://reviews.llvm.org/D150759
Files:
llvm/lib/Target/AMDGPU/VOP2Instructions.td
llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/never-uniform.mir
Index: llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/never-uniform.mir
===================================================================
--- llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/never-uniform.mir
+++ llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/never-uniform.mir
@@ -140,3 +140,26 @@
%5:vgpr_32 = V_AND_B32_e32 $vgpr4, $vgpr5, implicit $exec
S_ENDPGM 0
...
+# mbcnt instructions are not uniform
+---
+name: mbcnt_lo
+machineFunctionInfo:
+ isEntryFunction: true
+body: |
+ bb.0:
+ ; CHECK-LABEL: MachineUniformityInfo for function: mbcnt_lo
+ ; CHECK: DIVERGENT: %0
+ %0:vgpr_32 = V_MBCNT_LO_U32_B32_e64 -1, 0, implicit $exec
+ S_ENDPGM 0
+...
+---
+name: mbcnt_hi
+machineFunctionInfo:
+ isEntryFunction: true
+body: |
+ bb.0:
+ ; CHECK-LABEL: MachineUniformityInfo for function: mbcnt_hi
+ ; CHECK: DIVERGENT: %0
+ %0:vgpr_32 = V_MBCNT_HI_U32_B32_e64 -1, 0, implicit $exec
+ S_ENDPGM 0
+...
Index: llvm/lib/Target/AMDGPU/VOP2Instructions.td
===================================================================
--- llvm/lib/Target/AMDGPU/VOP2Instructions.td
+++ llvm/lib/Target/AMDGPU/VOP2Instructions.td
@@ -773,8 +773,10 @@
let isReMaterializable = 1 in {
defm V_BFM_B32 : VOP2Inst <"v_bfm_b32", VOP_I32_I32_I32>;
defm V_BCNT_U32_B32 : VOP2Inst <"v_bcnt_u32_b32", VOP_I32_I32_I32, add_ctpop>;
+let IsNeverUniform = 1 in {
defm V_MBCNT_LO_U32_B32 : VOP2Inst <"v_mbcnt_lo_u32_b32", VOP_I32_I32_I32, int_amdgcn_mbcnt_lo>;
defm V_MBCNT_HI_U32_B32 : VOP2Inst <"v_mbcnt_hi_u32_b32", VOP_I32_I32_I32, int_amdgcn_mbcnt_hi>;
+} // End IsNeverUniform = 1
defm V_LDEXP_F32 : VOP2Inst <"v_ldexp_f32", VOP_F32_F32_I32, AMDGPUldexp>;
let ReadsModeReg = 0, mayRaiseFPException = 0 in {
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