[llvm] 9602c7a - [AMDGPU][Uniformity] V_MBCNT* is never uniform

[Carl Ritson via llvm-commits]

Author: Carl Ritson
Date: 2023-05-18T13:50:12+09:00
New Revision: 9602c7a0817f34fb4d01194119fe4b75c00ea5ed

URL: https://github.com/llvm/llvm-project/commit/9602c7a0817f34fb4d01194119fe4b75c00ea5ed
DIFF: https://github.com/llvm/llvm-project/commit/9602c7a0817f34fb4d01194119fe4b75c00ea5ed.diff

LOG: [AMDGPU][Uniformity] V_MBCNT* is never uniform

Mark V_MBCNT instructions add thread/lane position so will never
be uniform.

Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D150759

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/VOP2Instructions.td
    llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/never-uniform.mir

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/VOP2Instructions.td b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
index 446e7d01c1d81..9442b1f960819 100644
--- a/llvm/lib/Target/AMDGPU/VOP2Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
@@ -773,8 +773,10 @@ def V_WRITELANE_B32 : VOP2_Pseudo<"v_writelane_b32", VOP_WRITELANE,
 let isReMaterializable = 1 in {
 defm V_BFM_B32 : VOP2Inst <"v_bfm_b32", VOP_I32_I32_I32>;
 defm V_BCNT_U32_B32 : VOP2Inst <"v_bcnt_u32_b32", VOP_I32_I32_I32, add_ctpop>;
+let IsNeverUniform = 1 in {
 defm V_MBCNT_LO_U32_B32 : VOP2Inst <"v_mbcnt_lo_u32_b32", VOP_I32_I32_I32, int_amdgcn_mbcnt_lo>;
 defm V_MBCNT_HI_U32_B32 : VOP2Inst <"v_mbcnt_hi_u32_b32", VOP_I32_I32_I32, int_amdgcn_mbcnt_hi>;
+} // End IsNeverUniform = 1
 defm V_LDEXP_F32 : VOP2Inst <"v_ldexp_f32", VOP_F32_F32_I32, AMDGPUldexp>;
 
 let ReadsModeReg = 0, mayRaiseFPException = 0 in {

diff  --git a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/never-uniform.mir b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/never-uniform.mir
index fa22890ec1d30..9a7e755e5f5c8 100644
--- a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/never-uniform.mir
+++ b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/never-uniform.mir
@@ -140,3 +140,26 @@ body:             |
     %5:vgpr_32 = V_AND_B32_e32 $vgpr4, $vgpr5, implicit $exec
     S_ENDPGM 0
 ...
+# mbcnt instructions are not uniform
+---
+name:            mbcnt_lo
+machineFunctionInfo:
+  isEntryFunction: true
+body:             |
+  bb.0:
+    ; CHECK-LABEL: MachineUniformityInfo for function: mbcnt_lo
+    ; CHECK: DIVERGENT: %0
+    %0:vgpr_32 = V_MBCNT_LO_U32_B32_e64 -1, 0, implicit $exec
+    S_ENDPGM 0
+...
+---
+name:            mbcnt_hi
+machineFunctionInfo:
+  isEntryFunction: true
+body:             |
+  bb.0:
+    ; CHECK-LABEL: MachineUniformityInfo for function: mbcnt_hi
+    ; CHECK: DIVERGENT: %0
+    %0:vgpr_32 = V_MBCNT_HI_U32_B32_e64 -1, 0, implicit $exec
+    S_ENDPGM 0
+...