[llvm] 5605582 - [X86]Fix wrong asm match for VMASKMOVDQU

[via llvm-commits]

Author: Wang, Xin10
Date: 2023-05-17T23:36:45-04:00
New Revision: 56055822b4d3a656ec0676de193c1065dc332188

URL: https://github.com/llvm/llvm-project/commit/56055822b4d3a656ec0676de193c1065dc332188
DIFF: https://github.com/llvm/llvm-project/commit/56055822b4d3a656ec0676de193c1065dc332188.diff

LOG: [X86]Fix wrong asm match for VMASKMOVDQU

VMASKMOVDQU supports 32bit/64bit version in 64bitmode, previously we prefer to use VMASKMOVDQU64 in 64bitmode because the 32bit one need 0x67 prefix.
After D150436, asm match table changed a little, which makes in 64bit mode "vmaskmovdqu     %xmm0, %xmm1" will match VMASKMOVDQU other than VMASKMOVDQU64, this patch correct the asm match order for this instruction.

Reviewed By: skan

Differential Revision: https://reviews.llvm.org/D150835

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86InstrSSE.td
    llvm/test/MC/X86/x86_64-asm-match.s

Removed: 
    


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diff  --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td
index 4296528bfc9bf..abb36e09db73f 100644
--- a/llvm/lib/Target/X86/X86InstrSSE.td
+++ b/llvm/lib/Target/X86/X86InstrSSE.td
@@ -4070,18 +4070,18 @@ let ExeDomain = SSEPackedInt, SchedRW = [SchedWriteVecMoveLS.XMM.MR] in {
 // As VEX does not have separate instruction contexts for address size
 // overrides, VMASKMOVDQU and VMASKMOVDQU64 would have a decode conflict.
 // Prefer VMASKMODDQU64.
-let Uses = [EDI], Predicates = [HasAVX], isAsmParserOnly = 1 in
-def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
-           (ins VR128:$src, VR128:$mask),
-           "maskmovdqu\t{$mask, $src|$src, $mask}",
-           [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>,
-           VEX, WIG;
 let Uses = [RDI], Predicates = [HasAVX,In64BitMode] in
 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
            (ins VR128:$src, VR128:$mask),
            "maskmovdqu\t{$mask, $src|$src, $mask}",
            [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>,
            VEX, WIG;
+let Uses = [EDI], Predicates = [HasAVX], isAsmParserOnly = 1 in
+def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
+           (ins VR128:$src, VR128:$mask),
+           "maskmovdqu\t{$mask, $src|$src, $mask}",
+           [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>,
+           VEX, WIG;
 
 let Uses = [EDI], Predicates = [UseSSE2] in
 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),

diff  --git a/llvm/test/MC/X86/x86_64-asm-match.s b/llvm/test/MC/X86/x86_64-asm-match.s
index f436fd2ded336..d4ec347901065 100644
--- a/llvm/test/MC/X86/x86_64-asm-match.s
+++ b/llvm/test/MC/X86/x86_64-asm-match.s
@@ -37,6 +37,11 @@
 // CHECK:   Matching formal operand class MCK_GR32 against actual operand at index 2 (Reg:ecx): match success using generic matcher
 // CHECK:   Matching formal operand class InvalidMatchClass against actual operand at index 3: actual operand index out of range
 // CHECK:   Opcode result: complete match, selecting this opcode
+// CHECK: AsmMatcher: found 2 encodings with mnemonic 'vmaskmovdqu'
+// CHECK: Trying to match opcode VMASKMOVDQU64
+// CHECK:   Matching formal operand class MCK_FR16 against actual operand at index 1 (Reg:xmm0): match success using generic matcher
+// CHECK:   Matching formal operand class MCK_FR16 against actual operand at index 2 (Reg:xmm1): match success using generic matcher
+// CHECK:   Matching formal operand class InvalidMatchClass against actual operand at index 3: actual operand index out of range
 // CHECK: AsmMatcher: found 4 encodings with mnemonic 'punpcklbw'
 // CHECK: Trying to match opcode MMX_PUNPCKLBWrr
 // CHECK:   Matching formal operand class MCK_VR64 against actual operand at index 1 (Reg:mm0): match success using generic matcher
@@ -51,6 +56,7 @@ pshufb    CPI1_0(%rip), %xmm1
 sha1rnds4 $1, %xmm1, %xmm2
 pinsrw    $3, %ecx, %xmm5
 crc32l    %gs:0xdeadbeef(%rbx,%rcx,8),%ecx
+vmaskmovdqu     %xmm0, %xmm1
 
 .intel_syntax
 punpcklbw mm0, dword ptr [rsp]