[PATCH] D150835: [X86]Fix wrong asm match for VMASKMOVDQU

[Wang, Xin via Phabricator via llvm-commits]

XinWang10 created this revision.
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XinWang10 requested review of this revision.
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Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D150835

Files:
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/test/MC/X86/x86_64-asm-match.s


Index: llvm/test/MC/X86/x86_64-asm-match.s
===================================================================
--- llvm/test/MC/X86/x86_64-asm-match.s
+++ llvm/test/MC/X86/x86_64-asm-match.s
@@ -37,6 +37,11 @@
 // CHECK:   Matching formal operand class MCK_GR32 against actual operand at index 2 (Reg:ecx): match success using generic matcher
 // CHECK:   Matching formal operand class InvalidMatchClass against actual operand at index 3: actual operand index out of range
 // CHECK:   Opcode result: complete match, selecting this opcode
+// CHECK: AsmMatcher: found 2 encodings with mnemonic 'vmaskmovdqu'
+// CHECK: Trying to match opcode VMASKMOVDQU64
+// CHECK:   Matching formal operand class MCK_FR16 against actual operand at index 1 (Reg:xmm0): match success using generic matcher
+// CHECK:   Matching formal operand class MCK_FR16 against actual operand at index 2 (Reg:xmm1): match success using generic matcher
+// CHECK:   Matching formal operand class InvalidMatchClass against actual operand at index 3: actual operand index out of range
 // CHECK: AsmMatcher: found 4 encodings with mnemonic 'punpcklbw'
 // CHECK: Trying to match opcode MMX_PUNPCKLBWrr
 // CHECK:   Matching formal operand class MCK_VR64 against actual operand at index 1 (Reg:mm0): match success using generic matcher
@@ -51,6 +56,7 @@
 sha1rnds4 $1, %xmm1, %xmm2
 pinsrw    $3, %ecx, %xmm5
 crc32l    %gs:0xdeadbeef(%rbx,%rcx,8),%ecx
+vmaskmovdqu     %xmm0, %xmm1
 
 .intel_syntax
 punpcklbw mm0, dword ptr [rsp]
Index: llvm/lib/Target/X86/X86InstrSSE.td
===================================================================
--- llvm/lib/Target/X86/X86InstrSSE.td
+++ llvm/lib/Target/X86/X86InstrSSE.td
@@ -4070,18 +4070,18 @@
 // As VEX does not have separate instruction contexts for address size
 // overrides, VMASKMOVDQU and VMASKMOVDQU64 would have a decode conflict.
 // Prefer VMASKMODDQU64.
-let Uses = [EDI], Predicates = [HasAVX], isAsmParserOnly = 1 in
-def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
-           (ins VR128:$src, VR128:$mask),
-           "maskmovdqu\t{$mask, $src|$src, $mask}",
-           [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>,
-           VEX, WIG;
 let Uses = [RDI], Predicates = [HasAVX,In64BitMode] in
 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
            (ins VR128:$src, VR128:$mask),
            "maskmovdqu\t{$mask, $src|$src, $mask}",
            [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>,
            VEX, WIG;
+let Uses = [EDI], Predicates = [HasAVX], isAsmParserOnly = 1 in
+def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
+           (ins VR128:$src, VR128:$mask),
+           "maskmovdqu\t{$mask, $src|$src, $mask}",
+           [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>,
+           VEX, WIG;
 
 let Uses = [EDI], Predicates = [UseSSE2] in
 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),


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